Datasheet

Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
94 Datasheet 298517-006
8.2 Signal Summaries
Table 52. Input Signals
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Always
BCLK High — System Bus Always
BCLK# Low — System Bus Always
BPRI# Low BCLK System Bus Always
DEFER# Low BCLK System Bus Always
FLUSH# Low Asynch CMOS Always
IGNNE# Low Asynch CMOS Always
INIT# Low Asynch System Bus Always
INTR High Asynch CMOS APIC disabled mode
LINT[1:0] High Asynch APIC APIC enabled mode
NMI High Asynch CMOS APIC disabled mode
NCTRL High Asynch
PICCLK High — APIC Always
PREQ# Low Asynch Implementation Always
PWRGOOD High Asynch Implementation Always
RESET# Low BCLK System Bus Always
RSP# Low BCLK System Bus Always
SMI# Low Asynch CMOS Always
STPCLK# Low Asynch Implementation Always
TCK High — JTAG
TDI TCK JTAG
TMS TCK JTAG
TRST# Low Asynch JTAG
VTTPWRGD High Asynch Power/Other
Table 53. Output Signals
Name Active Level Clock Signal Group
BSEL[1:0] High Asynch Open-drain
FERR# Low Asynch Open-drain
IERR# Low Asynch Open-drain
PRDY# Low BCLK Implementation
TDO High TCK JTAG
VID[4:0] High Asynch Power/Other