Datasheet

Mobile Intel

Celeron

Processor (0.13 µ)

Micro-FCBGA and Micro-FCPGA Packages Datasheet

298517-006 Datasheet 91

A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on

configuration. The configuration options are described in Section 4 and in the P6 Family of Processors

Developer’s Manual.

Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of

RESET#, the processor optionally executes its built-in self-test (BIST) and begins program execution at

reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the appropriate pins/balls on

both agents on the system bus.

RP# (I/O - AGTL)

The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the

system bus.

A correct parity signal is high if an even number of covered signals is low and low if an odd number of

covered signals are low. This definition allows parity to be high when all covered signals are high.

RS[2:0]# (I/O - AGTL)

The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for

completion of the current transaction) and must be connected to the appropriate pins/balls on both agents

on the system bus.

RSP# (I - AGTL)

The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for completion

of the current transaction) during assertion of RS[2:0]#. RSP# provides parity protection for RS[2:0]#.

RSP# should be connected to the appropriate pins/balls on both agents on the system bus.

A correct parity signal is high if an even number of covered signals are low, and it is low if an odd

number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high

since it is not driven by any agent guaranteeing correct parity.

RTTIMPEDP (I-Analog)

The RTTIMPEDP (R

Impedance/PMOS) signal is used to configure the on-die AGTL termination.

Connect the RTTIMPEDP signal to V

with a 56.2-Ω, 1% resistor.

SMI# (I - 1.5 V Tolerant)

The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a

System Management Interrupt, the processor saves the current state and enters System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution

from the SMM handler.

STPCLK# (I - 1.5 V Tolerant)

The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Quick

Start state. The processor issues a Stop Grant Acknowledge special transaction and stops providing

internal clock signals to all units except the bus and APIC units. The processor continues to snoop bus

transactions and service interrupts while in the Quick Start state. When STPCLK# is deasserted and