Datasheet

Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
90 Datasheet 298517-006
PICD[1:0] (I/O - 1.5 V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus.
They must be connected to the appropriate pins/balls of all APIC bus agents, including the processor and
the system logic or I/O APIC components. If the PICD0 signal is sampled low on the active-to-inactive
transition of the RESET# signal, then the APIC is hardware disabled. For the Mobile Intel Celeron
Processor, the APIC is required to be hardware enabled as described in Section 7.1.3.
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL. See
Section 3.2.2 for a description of the analog decoupling circuit.
PRDY# (O - AGTL)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5 V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processor.
PWRGOOD (I – 1.8 V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean
indication that clocks and the power supplies (V
CC
, V
CCT
, etc.) are stable and within their specifications.
Clean implies that the signal will remain low, (capable of sinking leakage current) and without glitches,
from the time that the power supplies are turned on, until they come within specification. The signal will
then transition monotonically to a high (1.8 V) state. Figure 15 through Figure 17 illustrate the
relationship of PWRGOOD to other system signals. PWRGOOD can be driven inactive at any time, but
clocks and power must again be stable before the rising edge of PWRGOOD. It must also meet the
minimum pulse width specified in Table 30 (Section 3.6) and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary
scan operation.
REQ[4:0]# (I/O - AGTL)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on both
agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]# to define
the currently active transaction type.
RESET# (I - AGTL)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2 caches
without writing back Modified (M state) lines. For a power-on type reset, RESET# must stay active for
at least 1 ms after V
CC
and BCLK, BCLK# have reached their proper DC and AC specifications and after
PWRGOOD has been asserted. When observing active RESET#, all bus agents will deassert their
outputs within two clocks. RESET# is the only AGTL signal that does not have on-die AGTL
termination. A 56.2 Ω 1% terminating resistor connected to V
CCT
is required.