Datasheet
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet 73
5.3 Signal Listings
Figure 31 is a top-side view of the ball or pin map of the Mobile Intel Celeron Processor with the voltage
balls/pins called out. Table 45 lists the signals in ball/pin number order. Table 46 lists the signals in
signal name order.
Figure 31. Pin/Ball Map - Top View
A10# VREF NC A31# BREQ0# A23# A27# A24# NC A35# A26# A33# A32# D0# D2# D15# D9# D7# VREF D8# D10# D11# VSS VCCT
NC VSS A25# VSS A17# VSS A21# VSS A20# VSS A18# VSS A34# VSS RESET# VSS D1# VSS D4# VSS D17# VSS D18# D14# D24# VSS
NC A16# A28# NC VCCT A19# VCCT A22# VCCT A30# VCCT A29# VCCT BERR# VCCT D6# VCCT D12# VCCT D5# VCCT NC VSS D20# VSS D30#
NC VSS A13# VSS VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D3# D13# D22# NC
NC TESTHI VCCT VCC VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D16# D23# VSS D19#
NC VSS A14# VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D21# D36# D27#
A9# A5# A15# VCCT VCC VSS VCC VSS VCCT D25# VSS D32#
A12# VSS A8# VSS VSS VCC VSS VCC VSS D26# D29# VREF
A4# A7# A11# VCCT VCC VSS VCC VSS VCCT D34# VSS D38#
A3# VSS A6# VSS VSS VCC VSS VCC VSS D31# D33# D35#
REQ4# BNR# REQ1# VCCT NC VSS VCC VSS VCCT D28# VSS D42#
VSS VSS VSS RSP# VCC VSS VCC VSS D39# D45# D48#
VREF PLL2 PLL1 NC VCC VSS VCC VSS VCCT NC VSS D37#
NC VSS API# NC NC VCC VSS VCC VSS D49# D41# NC
REQ0# BPRI# VID4 VSS VCC VSS VCC VSS VCCT D43# VSS D44#
REQ2# VSS DEFER# RP# VSS VCC VSS VCC VSS D47# D57# D51#
REQ3# HITM# RS2# VSS VCC VSS VCC VSS VCCT D52# VSS D40#
RS1# VSS LOCK# VCCT VSS VCC VSS VCC VSS D63# D46# D55#
TRDY# AERR# DBSY # VSS VCC VSS VCC VSS VCCT D59# VSS D54#
DRDY# VSS RS0# VSS VCC VSS VCC VSS D58# D53# D60#
VREF HIT# ADS# VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCCT D62# VSS D50#
VID0 VSS AP0#
PWR
GOOD
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D61# D56# VREF
BCLK VID1 A20M# VCCT VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCCT DEP3# VSS DEP6#
BCLK# /
CLKREF
VSS SMI# NC
CMOS
REF
VCCT TDI VCCT IGNNE# TCK TDO VCCT NC VCCT LINT0 NCTRL PICD1 VCCT PICD0 VCCT BPM1# BPM0# NC DEP7# DEP1# DEP5#
VSS VID2 VCCT STPCLK# VSS INIT# VSS NC VSS NC VSS BSEL0 VSS LINT1 VSS
RTT
IMPEDP
VSS VCCT VSS BP3# VSS PRDY# VSS DEP0# DEP2# VSS
VCCT VCCT VID3 IERR# FLUSH# FERR# TMS DPSLP# VREF BSEL1 TESTHI
CMOS
REF
THRMDATHRMDC
TRST#
EDGE
CTRLP
NC NC PREQ# PICCLK VREF BP2# BINIT# DEP4# VSS VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526
VTT
PWRGD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VCC VSS OtherVCCT
TESTLO
TESTLO
NC
Note : A2 pin is de-populated on Micro-FCPGA package