Datasheet

Mobile Intel

Celeron

Processor (0.13 µ)

Micro-FCBGA and Micro-FCPGA Packages Datasheet

298517-006 Datasheet 43

Table 26. System Bus Clock AC Specifications (133 MHz, Single Ended)

Symbol Parameter Min Max Unit Figure Notes

System Bus Frequency 133 MHz

T1S BCLK Period 7.5 7.65 ns 6 Note 2

T1Sabs BCLK Period – Instantaneous Minimum 7.25 Note 2

T2S BCLK Period Stability ±250 ps Notes 2, 3, 4

T3S BCLK High Time 1.4 ns 6 at>2.0 V

T4S BCLK Low Time 1.4 ns 6 at<0.5 V

T5S BCLK Rise Time 0.4 1.6 ns 6 Note 5

T6S BCLK Fall Time 0.4 1.6 ns 6 Note 5

NOTES:

1. All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25 V.

2. Period, jitter, skew and offset measured at 1.25 V.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a

component of BCLK skew between devices.

5. Measured between 0.5 V and 2.0 V.

Table 27. System Bus Clock AC Specifications (100 MHz, Single Ended)

Symbol Parameter Min Typ Max Unit Figure Notes

System Bus Frequency 100 MHz

T1S1 BCLK Period 10 ns 6 Note 2

T1S1abs BCLK Period – Instantaneous

Minimum

9.75 ns Note 2

T2S1 BCLK Period Stability ±250 ps Notes 2, 3, 4

T3S1 BCLK High Time 2.70 ns 6 at>2.0 V

T4S1 BCLK Low Time 2.45 ns 6 at<0.5 V

T5S1 BCLK Rise Time 0.4 1.6 ns 6 Note 5