Datasheet

Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
22 Datasheet 298517-006
The Open-drain output signals have open drain drivers and external pull-up resistors are required. One of
the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the
processor is functioning normally. The FERR# output can be either tri-stated or driven to V
SS
when the
processor is in a low-power state depending on the condition of the floating-point unit. Since this signal
is a DC current path when it is driven to V
SS
, Intel recommends that the software clears or masks any
floating-point error condition before putting the processor into the Deep Sleep state.
3.1.5.3 Other Signals
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states except the Deep
Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK and BCLK# are driven.
Otherwise, it is permitted to turn off PICCLK by holding it at V
SS
. BCLK and BCLK# should be obey
the DC levels in Table 38 (for Differential Clocking) and Table 39 (for Single Ended Clocking).
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus messages.
These signals are required to be tri-stated and pulled-up when the processor is in the Quick Start or Deep
Sleep states.
3.2 Power Supply Requirements
3.2.1 Decoupling Guidelines
The Mobile Intel Celeron Processor in Micro-FCPGA package has twelve 0805IDC, 1-µF surface mount
decoupling capacitors. Eight capacitors are on the V
CC
supply and four capacitors are on V
CCT.
For the
Micro-FCBGA package, there are six 0.68-µF capacitors on V
CC
and two 0.68-µF capacitors on V
CCT
. In
addition to the package capacitors, sufficient board level capacitors are also necessary for power supply
decoupling. The guidelines are as follows:
• High and Mid Frequency V
CC
decoupling – Place twenty-four 0.22-µF 0603 capacitors directly
under the package on the solder side of the motherboard using at least two vias per capacitor node.
Ten 10-µF X7 6.3V 1206-size ceramic capacitors should be placed around the package periphery
near the balls. Trace lengths to the vias should be designed to minimize inductance. Avoid
bending traces to minimize ESL.
• High and Mid Frequency V
CCT
decoupling – Place ten 1-µF X7R 0603 ceramic capacitors close to
the package. Via and trace guidelines are the same as above.
• Bulk V
CC
decoupling – Minimum of 1200-µF capacitance with Equivalent Series Resistance
(ESR) less than or equal to 3.5 mΩ.
• Bulk V
CCT
decoupling – Platform dependent but recommendation is minimum of 660 µF with ESR
less than or equal to 7 mΩ.
Please refer to the appropriate platform design guidelines for bulk decoupling recommendations.
3.2.2 Voltage Planes
All V
CC
and V
SS
pins/balls must be connected to the appropriate voltage plane. All V
CCT
and V
REF
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the main
V
CC
, V
CCT
, and V
SS
power supply signals, PLL1 and PLL2 provide analog decoupling to the PLL