User Manual

Mobile Intel
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Pentium
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4 Processor-M Datasheet 5
Figures
1 VCCVID Pin Voltage and Current Requirements ................................................15
2 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................17
3 Phase Lock Loop (PLL) Filter Requirements .....................................................18
4 Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................26
5 Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................28
6 Illustration of Deep Sleep VCC Static and Transient Tolerances (VID
Setting = 1.30 V) .................................................................................................29
7 ITPCLKOUT[1:0] Output Buffer Diagram ............................................................34
8 AC Test Circuit ....................................................................................................41
9 TCK Clock Waveform..........................................................................................41
10 Differential Clock Waveform................................................................................42
11 Differential Clock Crosspoint Specification..........................................................43
12 System Bus Common Clock Valid Delay Timings...............................................43
13 System Bus Reset and Configuration Timings....................................................44
14 Source Synchronous 2X (Address) Timings .......................................................44
15 Source Synchronous 4X Timings........................................................................45
16 Power Up Sequence ...........................................................................................46
17 Power Down Sequence.......................................................................................46
18 Test Reset Timings .............................................................................................47
19 THERMTRIP# to Vcc Timing...............................................................................47
20 FERR#/PBE# Valid Delay Timing .......................................................................47
21 TAP Valid Delay Timing ......................................................................................48
22 ITPCLKOUT Valid Delay Timing .........................................................................48
23 Stop Grant/Sleep/Deep Sleep Timing .................................................................49
24 Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................50
25 BCLK Signal Integrity Waveform.........................................................................52
26 Low-to-High System Bus Receiver Ringback Tolerance.....................................53
27 High-to-Low System Bus Receiver Ringback Tolerance.....................................53
28 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers.................................................................................................................54
29 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers.................................................................................................................54
30 Maximum Acceptable Overshoot/Undershoot Waveform ...................................59
31 Micro-FCPGA Package Top and Bottom Isometric Views ..................................61
32 Micro-FCPGA Package Top and Side View........................................................62
33 Micro-FCPGA Package - Bottom View................................................................64
34 The Coordinates of the Processor Pins as Viewed From the Top of the
Package. .............................................................................................................65
35 Clock Control States............................................................................................94