User Manual

Electrical Specifications
Mobile Intel

Pentium

4 Processor-M Datasheet 39
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*V
CC
at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at 0.5*V
CC
at the processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specifications for a minimum swing defined between TAP V
T-
to V
T+
. This assumes a minimum edge rate of
0.5 V/ns
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 25. ITPCLKOUT[1:0] AC Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.
Table 24. TAP Signals AC Specifications
Parameter Min Max Unit Figure Notes
1,2,3
T55: TCK Period 60.0 ns 9
T56: TCK Rise Time 10.0 ns 9 4
T57: TCK Fall Time 10.0 ns 9 4
T58: TMS Rise Time 8.5 ns 9 4
T59: TMS Fall Time 8.5 ns 9 4, 9
T61: TDI Setup Time 0 ns 21 5, 7
T62: TDI Hold Time 3 ns 21 5, 7
T63: TDO Clock to Output Delay 3.5 ns 21 6
T64: TRST# Assert Time 2 TCK 18 8, 9
Parameter Min Typ Max Unit Figure Notes
1,2
T65: ITPCLKOUT Delay 400 560 ps 22 3
T66: Slew Rate 2 8 V/ns
T67: ITPCLKOUT[1:0] High
Time
3.89 5 6.17 ns
T68: ITPCLKOUT[1:0] Low
Time
3.89 5 6.17 ns