User Manual

Introduction
Mobile Intel

Pentium

4 Processor-M Datasheet 11
1.1 Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
“System Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The system bus is a multiprocessing interface to processors, memory, and I/O.
Commonly used terms are explained here for clarification:
• Processor — For this document, the term processor shall mean the Mobile Intel Pentium 4
Processor-M in the 478-pin package.
• Keep out zone — The area on or near the processor that system design can not utilize.
• Intel

845MP/845MZ chipsets — Mobile chipsets that will support the Mobile Intel
Pentium 4 Processor-M.
• Processor core — Mobile Intel Pentium 4 Processor-M core die with integrated L2 cache.
• Micro-FCPGA package — Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch.
1.2 References
Material and concepts available in the following documents may be beneficial when reading this
document.
Table 1. References
Document Order Number
Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset
Platform Design Guide
250688-002
Intel Architecture Software Developer's Manual
Volume I: Basic Architecture 245470
Volume II: Instruction Set Reference 245471
Volume III: System Programming Guide 245472