Service Guide

BIOS Setup Utilities
134 Intel
®
Server System P4000IP and Intel
®
Workstation System P4000CR Service Guide
Comments: Information only. Displays whether the current DIMM configuration is
capable of Rank Sparing. For Rank Sparing to be possible, DIMM configurations on all
channels must be capable of supporting Rank Sparing.
Note
: The Correctable Error Threshold value is also the Sparing Fail Over threshold value.
Threshold values of “All” or “None” are not valid for Rank Sparing. If the Correctable Error
Threshold is set to either of those values, Rank Spring will not be possible.
3. Memory Lockstep Possible
Option Values: Yes
No
Help Text: <None>
Comments: Information only. Displays whether the current DIMM configuration is
capable of Memory Lockstep. For Memory Lockstep to be possible, DIMM configurations on
all paired channels must be identical between the channel pair.
4. Select Memory RAS Configuration
Option Values:
Maximum Performance
Mirroring
Rank Sparing
Lockstep
Help Text:
Allows the user to select the memory RAS Configuration to be applied for the next
boot.
Comments: Available modes depend on the current memory population. Modes which are not
listed as “possible” should not be available as choices. If the only valid choice is “Maximum
Performance”, then this option should be grayed out and unavailable.
Maximum Performance
– (default) no RAS, but best memory utilization since full
amount of memory is available, operating in Independent Channel Mode.
Mirroring
- most reliability by using half of memory as a mirror image, can survive an
Uncorrectable ECC Error.
Rank Sparing
– offers reliability by reserving spare ranks to replace failing ranks
which are generating excessive Correctable ECC Errors.
Lockstep
– allows SDDC capability with x8 DIMMs installed. No memory size impact,
but does have a performance and power penalty.
Note
: Since only RAS Modes which are listed as “possible” are available for
selection, it is not possible to select a RAS Mode without first installing an
appropriate DIMM configuration.