Intel I/O Expansion Modules for Intel platforms hardware specification

Dual Port Intel® 82599 10GbE I/O Module Intel® I/O Expansion Modules for Intel® Platforms HWS
5.4
Intel
®
82599 10Gb Ethernet Controller
1. General
 Serial Flash Interface
 4-wire SPI EEPROM Interface
 Protected EEPROM space for private configuration
 Device disable capability
 Package Size - 25 mm x 25 mm
2. Networking
 Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap (KX/KX4/KR) specification
 Complies with the 10 Gb/s Ethernet/802.3ae (XAUI) specification
 Complies with the 1000BASE-BX specification
 Complies with the IEEE 802.3x 100BASE-TX specification
 Support for jumbo frames of up to 15.5 KB
 Auto negotiation Clause 73 for supported mode
 CX4 per 802.3ak
 Flow control support: send/receive pause frames and receive FIFO thresholds
 Statistics for management and RMON
 802.1q VLAN support
 TCP segmentation offload: up to 256 KB
 IPv6 support for IP/TCP and IP/UDP receive checksum offload
 Fragmented UDP checksum offload for packet reassembly
 Message Signaled Interrupts (MSI)
 Message Signaled Interrupts (MSI-X)
 Interrupt throttling control to limit maximum interrupt rate and improve CPU usage
 Receive packet split header
 Multiple receive queues (Flow Director) 16 x 8 and 32 x 4
 128 transmit queues
 Receive header replication
 Dynamic interrupt moderation
 DCA support
 TCP timer interrupts
 NO snoop
 Relaxed ordering
 Support for 64 virtual machines per port (64 VMs x 2 queues)
 Support for Data Center Bridging (DCB) (802.1Qaz, 802.1Qbb, 802.1p)
3. Host Interface
 PCIe Base Specification 2.0 (2.5GT/s) or (5GT/s)
 Bus width — x1, x2, x4, x8
 64-bit address support for systems using more than 4 GB of physical memory
4. MAC Functions
 Descriptor ring management hardware for transmit and receive
 ACPI register set and power down functionality supportingD0 and D3 states
 A mechanism for delaying/reducing transmit interrupts
 Software-controlled global reset bit (resets everything except the configuration registers)
 Eight Software-Definable Pins (SDP) per port
 Four of the SDP pins can be configured as general-purpose interrupts
Revision 1.2
Intel order number: G30021-004
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