Technical Product Specification

Intel® Server Boards S4600LH2/T2 TPS
Revision 2.0
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3.2.3.2 Platform Configuration Structure
The DMI2 physically connects the processor and the PCH. From a configuration standpoint the DMI2 is a
logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically
constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH
appear to be on PCI Bus 0.
3.2.3.2.1 Processor IIO Devices (CPUBUSNO (0))
The processor IIO contains 10 PCI devices within a single, physical component. The configuration
registers for the devices are mapped as devices residing on PCI Bus “CPUBUSNO(0) ” where
CPUBUSNO(0) is programmable by BIOS.
Figure 12. Processor Integrated I/O Device Map
• Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI
Bus 0. Device 0 contains the standard PCI header registers, extended PCI
configuration registers and DMI2 device specific configuration registers.
• Device 1: PCI Express Root Port 1a and 1b. Logically this appears as a “virtual” PCI-to-PCI bridg
e
residing on PCI Bus 0 and is compliant with the PCI Express Local Bus Specification Revision 2.0.
Device 1 contains the standard PCI Express/PCI configuration registers including PCI Express Memory
Address Mapping registers. It also contains the extended PCI Express configuration space that include
PCIExpress error status/control registers and Isochronous and Virtual Channel controls.
• Device 2: PCI Express Root Port 2a, 2b, 2c and 2d. Logically this appears as a “virtual” PCI-to-PCI
bridge residing on PCI bus 0 and is compliant with PCI Express Specification Revision 2.0. Device 2
contains the standard PCI Express/PCI configuration registers including PCI
Express Memory Address
Mapping registers. It also contains the extended PCI Express configuration space that include PCI
Express Link status/control registers and Isochronous and Virtual Channel controls
• Device 3: PCI Express Root Port 3a, 3b, 3c and 3d. Logically this appears as a “virtual” PCI-to-PCI
bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus Specification Revision 2.0.