Technical Product Specification

Intel® Server Boards S4600LH2/T2 TPS

Revision 2.0

• Intel

Intelligent Power Technology

• Data Direct I/O (DDIO)

• Enhanced Intel

SpeedStep Technology

3.2.1 Intel

QuickPath Interconnect

The Intel

QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the

processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated

I/O platform architecture. It offers much higher bandwidth with low latency. The Intel

QuickPath Interconnect

has an

efficient

architecture

allowing more interconnect performance to be achieved in real systems. It has a

snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling

quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the

architecture.

The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a

differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the

connection between two components. This supports traffic in both directions simultaneously. To facilitate

flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and

Protocol.

The Intel

QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and

caching structures coherent during system operation. It supports both low-latency source snooping and a

scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal

latency.

3.2.2 Integrated Memory Controller (IMC) and Memory Subsystem

Figure 7. Integrated Memory Controller Functional Block Diagram