Technical Product Specification

BIOS Setup Interface Intel® Server Board S1600JP TPS
Setup Item
Options
Help Text
Comments
Current
Configuration
Independent
Channel
Mirror
Rank Sparing
Lockstep
None
Information only: Displays one of the
following:
Independent Channel – DIMMs are operating
in Independent Channel Mode, the default
configuration when there is no RAS Mode
configured.
Mirror – Mirroring RAS Mode has been
configured and is operational.
Rank Sparing – Rank Sparing RAS Mode has
been configured and is operational.
Lockstep – Lockstep RAS Mode has been
configured and is operational.
Current
Memory Speed
Operational
Memory Speed in
MT/s
None
Information only. Displays the speed in MT/s
at which the memory is currently running.
The supported memory speeds are 800 MT/s,
1066 MT/s, 1333 MT/s, and 1600 MT/s. The
actual memory speed capability depends on
the memory configuration.
Memory
Operating
Speed
Selection
Auto
800
1066
1333
1600
Force specific Memory
Operating Speed or use Auto
setting.
Allows the user to select a specific speed at
which memory will operate. Only speeds that
are legitimate are available, that is, the user
can only specify speeds less than or equal to
the auto-selected Memory Operating Speed.
The default Auto setting will select the highest
achievable Memory Operating Speed
consistent with the DIMMs and processors
installed.
Phase
Shedding
Enabled
Disabled
Enable/disable DDR3 VR
Static Phase Shedding. When
enabled, DDR3 VR can be
automatically adjusted by
typical load.
This feature helps DDR3 VR optimize for high
loading.
Memory SPD
Override
Enabled
Disabled
When enabled, it extends the
platform’s capability to support
higher Memory Frequency
than the POR Settings;
Disabling it keeps the POR
settings.
None
Patrol Scrub
Enabled
Disabled
When enabled, performs
periodic checks on memory
cells and proactively walks
through populated memory
space, to seek and correct
soft ECC errors.
When enabled, Patrol Scrub is initialized to
read through all of memory in a 24-hour
period, correcting any Correctable ECC
Errors it encounters by writing back the
corrected data to memory.
84 Revision 1.9