Technical Product Specification

Intel® Server Board S1600JP TPS Product Architecture Overview
 Command launch modes of 1n/2n.
 RAS Support:
o Rank Level Sparing and Device Tagging.
o Demand and Patrol Scrubbing.
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode.
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in
lockstep mode.
o Data scrambling with address to ease detection of write errors to an
incorrect address.
o Error reporting through Machine Check Architecture.
o Read Retry during CRC error handling checks by iMC.
o Channel mirroring within a socket.
o Error Containment Recovery.
o Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling
(CLTT).
 Memory thermal monitoring support for DIMM temperature.
3.3.1.1
Supported Memory
Supported and validated
Support but not validated
Supported with limited validation
Table 3. Intel
®
Xeon
®
processor E5-2600, E5-2600 v2, E5-1600, and E5-1600 v2 product family
UDIMM Support Guidelines
Ranks Per DIMM
and Data Width
Memory Capacity Per
DIMM
1
Speed (MT/s) and Voltage Validated by Slot Per Channel (SPC)
and DIMM Per Channel (DPC)
2
2 Slots Per Channel
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
SRx8
ECC
1GB 2GB 4GB 1066, 1333
1066, 1333,
1600, 1866
1066, 1333
1066, 1333,
1600
DRx8
ECC
2GB 4GB 8GB 1066, 1333
1066, 1333,
1600, 1866
1066, 1333
1066, 1333,
1600
Notes:
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