Technical Product Specification

Product Architecture Overview Intel® Server Board S1600JP TPS
 A 32-KB instruction and 32-KB data first-level cache (L1) for each core.
 A 256-KB shared instruction/data mid-level (L2) cache for each core.
 Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores.
Supported Technologies:
 Intel
®
Virtualization Technology (Intel
®
VT)
 Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
 Intel
®
Virtualization Technology s
 Intel
®
Trusted Execution Technology (Intel
®
TXT)
 Intel
®
64 Architecture
 Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
 Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
 Intel
®
Advanced Vector Extensions (Intel
®
AVX)
 Intel
®
Hyper-Threading Technology
 Execute Disable Bit
 Intel
®
Turbo Boost Technology
 Intel
®
Intelligent Power Technology
 Enhanced Intel
®
SpeedStep Technology
3.3.1
Integrated Memory Controller (IMC) and Memory Subsystem
 Unbuffered DDRIII and registered DDRIII DIMMs.
 LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems.
 Independent channel mode or lockstep mode.
 Data burst length of eight cycles for all memory organization modes.
 Memory DDRIII data transfer rates of 800, 1066, 1333, 1600, and 1866 MT/s.
 64-bit wide channels plus 8-bits of ECC support for each channel.
 DDRIII standard I/O Voltage of 1.5V for all speed.
 DDRIII Low Voltage of 1.35V for 1333MT/s or below.
 1-Gb, 2-Gb, and 4-Gb DDRIII DRAM technologies supported for these devices:
o UDIMM DDRIII – SR x8 and x16 data widths, DR – x8 data width.
o RDIMM DDRIII – SR, DR, and QR – x4 and x8 data widths.
o LRDIMM DDRIII – QR – x4 and x8 data widths with direct map or with
rank multiplication.
 Up to 8 ranks supported per memory channel, 1, 2, or 4 ranks per DIMM.
 Open with adaptive idle page close timer or closed page policy.
 Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern.
 Isochronous access support for Quality of Service (QoS).
 Minimum memory configuration: Independent channel support with one DIMM populated
 Integrated dual SMBus* master controllers.
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