Technical Product Specification

Platform Management Functional Overview Intel® Server Board S1600JP TPS
4.14
Management Engine (ME)
4.14.1
Overview
The Intel
®
Server Platform Services (SPS) is a set of manageability services provided by the
firmware executing on an embedded ARC controller within the IOH. This management controller
is also commonly referred to as the Management Engine (ME). The functionality provided by the
SPS firmware is different from Intel
®
Active Management Technology (Intel
®
AMT or AT)
provided by the ME on client platforms.
Server Platform Services (SPS) are value-added platform management options that enhance
the value of Intel
®
platforms and their component ingredients (CPUs, chipsets, and I/O
components). Each service is designed to function independently wherever possible, or grouped
together with one or more features in flexible combinations to allow OEMs to differentiate
platforms.
4.14.2
BMC – Management Engine (ME) Distributed Model
The Intel
®
Server Board S1600JP covered in this specification will require Node Manager 2.0
(NM2.0) support.
The following management architecture would need to be supported on the
baseboard to meet product and validation requirements. The NM 2.0 functionality is provided by
the Intel
®
C600 PCH Management Engine (ME).
The server management architecture is a partitioned model which places the Management
Engine, which is an embedded controller in the Intel
®
C600 PCH, in between the BMC and the
processors. In this architecture, the PCH Management Engine is the owner of the PECI 3.0 bus
and the Emulex* Pilot III BMC communicates with the ME through a SMBus* connection
(SMLINK 0.)
The ME provides PECI proxy support that allows the ServerEngines* Pilot III BMC
firmware to access processor functions available on the PECI bus.
The primary function of ME is to implement the NM 2.0 feature set. In this architectural model,
the Emulex* Pilot III BMC provides the external (LAN) interface to ME in the form of IPMI
bridging.
A remote Node Manager application would establish a management session with the
Emulex* Pilot III BMC which in turn would bridge IPMI commands through the secondary IPMB
to the ME.
In this scenario, the Emulex* Pilot III BMC simply acts as a proxy for this
communication pipe.
The ME may also generate alerts to the Emulex* Pilot III BMC, which may
log these into the system SEL and/or output them to the remote application in the form of IPMI
LAN alerts.
The Emulex* Pilot III BMC needs access to various system registers in the processor core
silicon and integrated memory controller subsystem.
Examples include Processor core and
Memory DIMMs temperature information.
The Emulex* Pilot III BMC requires this information as
input into its fan speed control algorithms.
The Emulex* Pilot III BMC accesses these registers
through the secondary IPMB bus connection to ME. Depending on the particular data or register
access needed, this is done using either the ME’s PECI proxy functionality or through an
abstracted data construct provided by the ME.
Also in this architecture, both the Emulex* Pilot III BMC and the ME are connected to the
system power supplies through a common PMBus* (SMBUS* physical) connection (SMLINK 1.)
The ME accesses the system power supplies in support of various NM 2.0 features. The
Emulex* Pilot III BMC monitors the power supplies in support of various power-related telemetry
and status information that is exposed as IPMI sensors.
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