Technical Product Specification

Platform Management Functional Overview Intel® Server Board S1600JP TPS
State
Supported
Description
S1
Yes
Sleeping. Hardware context is maintained; equates to processor and chipset clocks being
stopped.
 The front panel power LED blinks at a rate of 1 Hz with a 50% duty cycle (not controlled
by the BMC).
 The watchdog timer is stopped.
 The power, reset, front panel NMI, and ID buttons are unprotected.
 Fan speed control is determined by available SDRs. Fans may be set to a fixed state, or
basic fan management can be applied.
The BMC detects that the system has exited the ACPI S1 sleep state when the BIOS SMI
handler notifies it.
S2
No
Not supported.
S3
No
Supported only on Workstation platforms. See appropriate Platform Specific Information for
more information.
S4
No
Not supported.
S5
Yes
Soft off.
 The front panel buttons are not locked.
 The fans are stopped.
 The power-up process goes through the normal boot process.

The power, reset, front panel NMI, and ID buttons are unlocked.
4.3
Platform Management SMBus* and I
2
C Implementation
SMBus*/ I
2
C interconnections are a fundamental interface for various manageability
components. There are three buses that are used in a multi-master fashion.
 Primary IPMB. An IPMB header is provided on the baseboard to support connectivity
with third-party management PCIe cards. This bus operates as 100 kHz bus.
 Secondary IPMB. This is the SMLink0 bus that connects the BMC with the ME in the
SSB. This bus is considered a secondary IPMB. The ME and BMC communicate over
this bus using IPMB protocol messages. Any devices on the bus must be 400 kHz
bus tolerant.
 PMBus*. This is the SMLink1 bus that both the ME and BMC use to communicate with
the power supplies. This bus operates as 100 kHz bus.
For all multi-master buses, the master that initiates a transaction is responsible for any bus
recovery sequence if the bus hangs.
The BMC acts as master for the other buses connected to it.
4.4
BMC Internal Timestamp Clock
The BMC maintains an internal timestamp clock that is used by various BMC subsystems, for
example, for time stamping SEL entries. As part of BMC initialization after AC power is applied
or the BMC is reset, the BMC initializes this internal clock to the value retrieved from the SSB
component’s RTC through a SMBus* slave read operation. This is the system RTC and is on
the battery power well so it maintains the current time even when there is no AC supplied to
the system.
The BMC reads the RTC using the same SMBus* (the “host SMBus*”) that is used by BIOS
during POST, so the BMC FW must not attempt to access the RTC between the time the
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