Technical Product Specification

Intel® Server Board S1600JP TPS Product Architecture Overview
3.4.4
PCI Interface
The Intel
®
C600 PCH PCI Interface provides a 33 MHz, Revision 2.3 implementation. It
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the PCH
internal requests. This allows for combinations of up to four PCI down devices and
PCI slots.
3.4.5
Low Pin Count (LPC) Interface
The Intel
®
C600 PCH implements an LPC Interface as described in the LPC 1.1 Specification.
The Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31: Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units including
DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.
3.4.6
Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Intel
®
C600 PCH. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current, and legacy software to operate normally.
3.4.7
Serials Peripheral Interface (SPI)
The Intel
®
C600 PCH implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required to
support Gigabit Ethernet and Intel
®
Active Management Technology. The PCH supports up to
two SPI flash devices with speeds up to 50 MHz, utilizing two chip select pins.
3.4.8
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is
reserved as a generic bus master request.
The Intel
®
C600 PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and
special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 8254 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The Intel
®
C600 PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 8259 interrupt controllers. The two interrupt controllers are
cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH
supports a serial interrupt scheme. All of the registers in these modules can be read and
restored. This is required to save and restore system state after power has been removed and
restored to the platform.
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