Technical Product Specification

Product Architecture Overview Intel® Server Board S1600JP TPS
 All DIMMs must be DDRIII DIMMs.
 Unbuffered DIMMs can be ECC.
 Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
 Mixing of LRDIMM with any other DIMM type is not allowed per platform.
 Mixing of DDRIII voltages is not validated within a socket or across sockets by Intel
®
. If
1.35V (DDRIIIL) and 1.50V (DDRIII) DIMMs are mixed, the DIMMs will run at 1.50V.
 Mixing of DDRIII operating frequencies is not validated within a socket or across sockets
by Intel
®
. If DIMMs with different frequencies are mixed, all DIMMs will run at the
common lowest frequency.
 Quad rank RDIMMs are supported but not validated by Intel
®
.
 A maximum of eight logical ranks (ranks seen by the host) per channel is allowed.
3.3.1.3
Publishing System Memory
 The BIOS displays the “Total Memory” of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDRIII DIMMs
in the system.
 The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDRIII DIMMs that are active (not disabled)
and not used as redundant units.
 The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.
 If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.
3.3.1.4
RAS Features
The server board supports the following memory RAS modes:
 Independent Channel Mode
 Rank Sparing Mode
 Mirrored Channel Mode
 Lockstep Channel Mode
Note that support of RAS modes that require matching DIMM population between channels
(Mirrored and Lockstep) require that ECC DIMMs be populated.
For RAS modes that require matching populations, the same slot positions across channels
must hold the same DIMM type with regards to size and organization. DIMM timings do not
have to match but timings will be set to support all the DIMMs populated (that is, DIMMs with
slower timings will force faster DIMMs to the slower common timing modes).
3.3.1.4.1 Independent Channel Mode
Channels can be populated in any order in Independent Channel Mode. All four channels may
be populated in any order and have no matching requirements. All channels must run at the
same interface frequency but individual channels may run at different DIMM timings (RAS
latency, CAS latency, and so forth).
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