Technical Product Specification
Intel® Server Board S1600JP TPS Power Supply Specification Guidelines
between power supplies (passive sharing).
The 12VSB output of the power supplies are
connected together in the system so that a failure or hot swap of a redundant power supply
does not cause these outputs to go out of regulation in the system.
10.2.14
Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors.
A
10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor is placed at the point
of measurement.
Table 92. 750W Ripples and Noise
+12V main +12VSB
120mVp-p
120mVp-p
10.2.15
Timing Requirement
These are the timing requirements for the power supply operation.
The output voltages must rise
from 10% to within regulation limits (T
vout_rise
) within 5ms to 70ms. For 12VSB, it is allowed to
rise from 1.0ms to 25ms.
All outputs must rise monotonically. The following table shows the
timing requirements for the power supply being turned on and off through the AC input, with
PSON held low and the PSON signal, with the AC input applied.
Table 93. 750W Timing Requirements
Item
Description
Min
Max
Units
T
vout_rise
Output voltage rise time.
5.0 *
70 *
ms
T
sb_on_delay
Delay from AC being applied to 12VSB being within
regulation.
1500 ms
T
ac_on_delay
Delay from AC being applied to all output voltages being
within regulation.
3000
ms
T
vout_holdup
Time 12Vl output voltage stay within regulation after loss
of AC.
13
ms
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK.
12
ms
T
pson_on_delay
Delay from PSON# active to output voltages within
regulation limits.
5
400
ms
T
pson_pwok
Delay from PSON# deactivate to PWOK being de-
asserted.
5
ms
T
pwok_on
Delay from output voltages within regulation limits to
PWOK asserted at turn on.
100
500
ms
T
pwok_off
Delay from PWOK de-asserted to output voltages
dropping out of regulation limits.
1 ms
T
pwok_low
Duration of PWOK being in the de-asserted state during
an off/on cycle using AC or the PSON signal.
100 ms
T
sb_vout
Delay from 12VSB being in regulation to O/Ps being in
regulation at AC turn on.
50
1000
ms
T
12VSB_holdup
Time the 12VSB output voltage stays within regulation
after loss of AC.
70
ms
Note:
* The 12VSB output voltage rise time shall be from 1.0ms to 25ms.
Revision 1.9 179