S2600GZ and S2600GL

Product Architecture Overview Intel® Server Board S2600GZ/GL TPS
3.2.4.4.3
Mirror Mode
Memory mirroring mode is the mechanism by which a component of memory is mirrored. In mirrored mode,
when a write is performed to one copy, a write is generated to the target location as well. This guarantees that
the target is always updated with the latest data from the main copy. The iMC module supports mirroring
across the corresponding mirroring channel within the processor socket but not across sockets. DIMM
organization in each slot of one channel must be identical to the DIMM in the corresponding slot of the other
channel. This allows a single decode for both channels. When mirroring mode is enabled, memory image in
Channel 0 is maintained the same as Channel 1 and Channel 2 is maintained the same as Channel 3.
3.2.4.5
Memory RAS Support
The server board supports the following memory RAS modes:
 Single Device Data Correction (SDDC)
 Error Correction Code (ECC) Memory
 Demand Scrubbing for ECC Memory
 Patrol Scrubbing for ECC Memory
 Rank Sparing Mode
 Mirrored Channel Mode
 Lockstep Channel Mode
Regardless of RAS mode, the requirements for populating within a channel given in the section 3.2.2.2 must
be met at all times. Note that support of RAS modes that require matching DIMM population between channels
(Mirrored and Lockstep) require that ECC DIMMs be populated. Independent Channel Mode is the only mode
that supports non-ECC DIMMs in addition to ECC DIMMs.
For Lockstep Channel Mode and Mirroring Mode, processor channels are paired together as a “Domain”.
 CPU1 Mirroring/Lockstep Domain 1 = Channel A + Channel B
 CPU1 Mirroring/Lockstep Domain 2 = Channel C + Channel D
 CPU2 Mirroring/Lockstep Domain 1 = Channel E + Channel F
 CPU2 Mirroring/Lockstep Domain 2 = Channel G + Channel H
For RAS modes that require matching populations, the same slot positions across channels must hold the
same DIMM type with regards to size and organization. DIMM timings do not have to match but timings will be
set to support all DIMMs populated (that is, DIMMs with slower timings will force faster DIMMs to the slower
common timing modes).
3.2.4.5.1
Single Device Data Correction (SDDC)
SDDC – Single Device Data Correction is a technique by which data can be replaced by the IMC from an
entire x4 DRAM device which is failing, using a combination of CRC plus parity. This is an automatic IMC
driven hardware. It can be extended to x8 DRAM technology by placing the system in Channel Lockstep Mode.
3.2.4.5.2
Error Correction Code (ECC) Memory
ECC uses “extra bits” – 64-bit data in a 72-bit DRAM array – to add an 8-bit calculated “Hamming Code” to
each 64 bits of data. This additional encoding enables the memory controller to detect and report single or
multiple bit errors when data is read, and to correct single-bit errors.
3.2.4.5.2.1 Correctable Memory ECC Error Handling
A “Correctable ECC Error” is one in which a single-bit error in memory contents is detected and corrected by
use of the ECC Hamming Code included in the memory data. For a correctable error, data integrity is
preserved, but it may be a warning sign of a true failure to come. Note that some correctable errors are
expected to occur.
Revision 2.4
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