S2600GZ and S2600GL

Intel® Server Board S2600GZ/GL TPS Product Architecture Overview
The following sections will provide an overview of the key processor features and functions that help to define
the architecture, performance and supported functionality of the server board. For more comprehensive
processor specific information, refer to the Intel
®
Xeon
®
processor E5-2600 product family documents listed in
the Reference Documents list.
3.2.1
Processor Core Features:
 Up to 8 execution cores (Intel
®
Xeon
®
processor E5-2600 product family)
 Up to 12 execution cores (Intel
®
Xeon
®
processor E5-2600 v2 product family)
 Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket
 46-bit physical addressing and 48-bit virtual addressing
 1 GB large page support for server applications
 A 32-KB instruction and 32-KB data first-level cache (L1) for each core
 A 256-KB shared instruction/data mid-level (L2) cache for each core
 Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC),
shared among all cores
3.2.2
Supported Technologies:
 Intel
®
Virtualization Technology (Intel
®
VT)
 Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
 Intel
®
Virtualization Technology Processor Extensions
 Intel
®
Trusted Execution Technology (Intel
®
TXT)
 Intel
®
64 Architecture
 Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
 Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
 Intel
®
Advanced Vector Extensions (Intel
®
AVX)
 Intel
®
Hyper-Threading Technology
 Execute Disable Bit
 Intel
®
Turbo Boost Technology
 Intel
®
Intelligent Power Technology
 Data Direct I/O (DDIO)
 Enhanced Intel
®
SpeedStep Technology
3.2.3
Intel
®
QuickPath Interconnect
The Intel
®
QuickPath Interconnect (QPI) is a high speed, packetized, point-to-point interconnect used in the
processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated
I/O platform architecture. It offers much higher bandwidth with low latency. The Intel
®
QuickPath Interconnect
has an
efficient architecture allowing more interconnect performance to be achieved in real systems. It has a
snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling
quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the
architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a
differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the
connection between two components. This supports traffic in both directions simultaneously. To facilitate
flexibility and longevity, the inter-connect is defined as having five layers: Physical, Link, Routing, Transport, and
Protocol.
The Intel
®
QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and
caching structures coherent during system operation. It supports both low-latency source snooping and a
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