Intel Server Board S2400BB

Intel® Server Board S2400BB TPS
Revision 2.0
21
3.2.2.8.1 Correctable Memory ECC Error Handling
A “Correctable ECC Error” is one in which a single-bit error in memory contents is detected and corrected by
use of the ECC Hamming Code included in the memory data. For a correctable error, data integrity is
preserved, but it may be a warning sign of a true failure to come. Note that some correctable errors are
expected to occur.
The system BIOS has logic to cope with the random factor in correctable ECC errors. Rather than reporting
every correctable error that occurs, the BIOS has a threshold and only logs a correctable error when a
threshold value is reached. Additional correctable errors that occur after the threshold has been reached are
disregarded. In addition, on the expectation the server system may have extremely long operational runs
without being rebooted, there is a “Leaky Bucket” algorithm incorporated into the correctable error counting
and comparing mechanism. The “Leaky Bucket” algorithm reduces the correctable error count as a function of
time – as the system remains running for a certain amount of time, the correctable error count will “leak out” of
the counting registers. This prevents correctable error counts from building up over an extended runtime.
The correctable memory error threshold value is a configurable option in the <F2> BIOS Setup Utility, where
you can configure it for 20/10/5/ALL/None
Once a correctable memory error threshold is reached, the event is logged to the System Event Log (SEL) and
the appropriate memory slot fault LED is lit to indicate on which DIMM the correctable error threshold crossing
occurred.
3.2.2.8.2 Uncorrectable Memory ECC Error Handling
All multi-bit “detectable but not correctable“ memory errors are classified as Uncorrectable Memory ECC
Errors. This is generally a fatal error.
However, before returning control to the OS drivers via Machine Check Exception (MCE) or Non-Maskable
Interrupt (NMI), the Uncorrectable Memory ECC Error is logged to the SEL, the appropriate memory slot fault
LED is lit, and the System Status LED state is changed to a solid Amber.
3.2.2.9 Demand Scrubbing for ECC Memory
Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is
detected on a read transaction. This allows for correction of data in memory at detect, and decrease the
chances of a second error on the same address accumulating to cause a multi-bit error (MBE) condition.
Demand Scrubbing is enabled/disabled (default is enabled) in the Memory Configuration screen in BIOS
Setup.
3.2.2.10 Patrol Scrubbing for ECC Memory
Patrol scrubs are intended to ensure that data with a correctable error does not remain in DRAM long enough
to stand a significant chance of further corruption to an uncorrectable stage.
3.2.3 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset components.
The integrated I/O module provides the following features:
• PCI Express Interfaces: The integrated I/O module incorporates the PCI Express interface and
supports up to 40 lanes of PCI Express. Following are key attributes of the PCI Express interface:
o Gen3 speeds at 8 GT/s (no 8b/10b encoding)
o X16 interface bifurcated down to two x8 or four x4 (or combinations)
o X8 interface bifurcated down to two x4
• DMI2 Interface to the PCH: The platform requires an interface to the legacy Southbridge (PCH) which
provides basic, legacy functions required for the server platform and operating systems. Since only one