Intel Server Board S2400BB

Intel® Server Board S2400BB TPS
Revision 2.0
51
6.9.3 Memory Thermal Throttling
The server board provides support for system thermal management through open loop throttling (OLTT) and
closed loop throttling (CLTT) of system memory. Normal system operation uses closed-loop thermal throttling
(CLTT) and DIMM temperature monitoring as major factors in overall thermal and acoustics management. In
the event that BIOS is unable to configure the system for CLTT, it defaults to open-loop thermal throttling
(OLTT). In the OLTT mode, it is assumed that the DIMM temperature sensors are not available for fan speed
control.
Throttling levels are changed dynamically to cap throttling based on memory and system thermal conditions as
determined by the system and DIMM power and thermal parameters. The BMC’s fan speed control
functionality is linked to the memory throttling mechanism used.
The following terminology is used for the various memory throttling options:
 Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers that are configured by
BIOS MRC remain fixed after post. The system does not change any of the throttling control registers in
the embedded memory controller during runtime.
 Static Closed Loop Thermal Throttling (Static-CLTT): CLTT control registers are configured by BIOS
MRC during POST. The memory throttling is run as a closed-loop system with the DIMM temperature
sensors as the control input. Otherwise, the system does not change any of the throttling control registers
in the embedded memory controller during runtime.
 Dynamic Closed Loop Thermal Throttling (Dynamic-CLTT): CLTT control registers are configured by
BIOS MRC during POST. The memory throttling is run as a closed-loop system with the DIMM
temperature sensors as the control input. Adjustments are made to the throttling during runtime based on
changes in system cooling (fan speed).
Both Static and Dynamic CLTT modes implement a Hybrid Closed Loop Thermal Throttling mechanism
whereby the Integrated Memory Controller estimates the DRAM temperature in between actual reads of the
memory thermal sensors.
6.10 Messaging Interfaces
The BMC supports the following communications interfaces:
 Host SMS interface by means of low pin count (LPC)/keyboard controller style (KCS) interface
 Host SMM interface by means of low pin count (LPC)/keyboard controller style (KCS) interface
 Intelligent Platform Management Bus (IPMB) I2C interface
 LAN interface using the IPMI-over-LAN protocols
Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. The following tables shows the
standard channel assignments.