Intel Server Board S2400BB

Intel® Server Board S2400BB TPS

Revision 2.0

PCH is required and allowed for the system, any sockets which do not connect to PCH would use this

port as a standard x4 PCI Express 2.0 interface.

• Integrated IOAPIC: Provides support for PCI Express devices implementing legacy interrupt messages

without interrupt sharing

• Non Transparent Bridge: PCI Express non-transparent bridge (NTB) acts as a gateway that enables

high performance, low overhead communication between two intelligent subsystems; the local and the

remote subsystems. The NTB allows a local processor to independently configure and control the local

subsystem, provides isolation of the local host memory domain from the remote host memory domain

while enabling status and data exchange between the two domains.

• Intel

QuickData Technology: Used for efficient, high bandwidth data movement between two

locations in memory or from memory to I/O

Figure 12. Processor IIO Feature Interconnect Block Diagram

The following sub-sections will describe the server board features that are directly supported by the processor

IIO module. These include the Riser Card Slots, and support for the optional I/O modules. Features and

functions of the Intel

C600 Series chipset will be described in its own dedicated section.

Intel® C6

00 RAID Upgrade Key

Riser Slot 1

x16 PCIe Gen3 32GB/s

X24 PCIe Gen3

x16 PCIe Gen3

32GB/s

x4 PCIe Gen3

8GB/s

x4 PCIe Gen3

8GB/s

MUX

X8 PCIe Gen3

16GB/s

Riser Slot 2

DMI2 x4

Gen2 4GB/s

x4 PCIe with no 8-port Upgrade Key Installed

(Option) IO Module

Connector (15W)