Intel Server Board S2400BB

Intel® Server Board S2400BB TPS
Revision 2.0
18
• When single, dual and quad rank DIMMs are populated for 2DPC, always populate the higher number
rank DIMM first (starting from the farthest slot), for example, first quad rank, then dual rank, and last
single rank DIMM.
• Mixing of quad ranks DIMMs (RDIMM Raw Cards F and H) in one channel and two DIMMs in other
channel (2DPC) on the same CPU socket is not validated.
3.2.2.3 Publishing System Memory
 The BIOS displays the “Total Memory” of the system during POST if Quiet Boot is disabled in BIOS
setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the
individual sizes of installed DDR3 DIMMs in the system.
 The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term Effective Memory
refers to the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant
units.
 The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the
same as the amount described by the first bullet above.
 If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the
end of POST. This total is the same as the amount described by the first bullet above.
Note: Some server operating systems do not display the total physical memory installed. What is displayed is
the amount of physical memory minus the approximate memory space used by system BIOS components.
These BIOS components include, but are not limited to:
- ACPI (may vary depending on the number of PCI devices detected in the system)
- ACPI NVS table
- Processor microcode
- Memory Mapped I/O (MMIO)
- Manageability Engine (ME)
- BIOS flash
3.2.2.4 Integrated Memory Controller Operating Modes and RAS Support
The server board supports the following memory operating and RAS modes:
 Independent Channel Mode
 Lockstep Channel Mode
 Mirrored Channel Mode
 Rank Sparing Mode
 Single Device Data Correction (SDDC)
 Error Correction Code (ECC) Memory
 Demand Scrubbing for ECC Memory
 Patrol Scrubbing for ECC Memory
The requirements for populating DIMMS within a channel given in the section 3.2.2.2 must be met at all times.
Note that support of RAS modes that require matching DIMM population between channels (Mirrored and
Lockstep) require that ECC DIMMs be populated. Independent Channel Mode is the only mode that supports
non-ECC DIMMs in addition to ECC DIMMs. Note however that Intel does not support non-ECC DIMMs in its
server products.
For RAS modes that require matching populations, the same slot positions across channels must hold the
same DIMM type with regards to size and organization. DIMM timings do not have to match but timings will be