Personal Computer User Manual

Intel® PXA27x Processor Family Power Requirements

Application Note 31

6.3 Power Manager I

C Interface

The PXA27x processor communicates with the PMIC using the I

C serial bus. The flexible I

controller in the processor can pre-load a buffer with a series of commands, or multi-byte

commands of any size, up to a total of 32 bytes of command address and data. The I

C controller

can be programmed to send a series of commands with programmable intervals between groups of

commands to accommodate a variety of different power controllers and regulators.

Refer to the Intel® PXA27x Processor Family EMTS for voltage change timing specifications.

The I

C interface runs in either standard mode at 40 kHz or fast mode at 160 kHz using standard 7-

bit addressing. The hardware general call and 10-bit extended addressing are not supported.

6.4 DVM Sequencing

The PMIC contains registers that enable, at a minimum, these functions:

• Programming a voltage change from the current voltage to a new voltage

• Programming a ramp rate at which the voltage change occurs

• A GO bit, which once set, triggers the requested voltage change

7.0 Fault Management

The PXA27x processor provides two digital status inputs (nBATT_FAULT and nVDD_FAULT)

driven by the external PMIC that indicate status of the main battery and the power-supply

regulators. These signals permit a combination of hardware and software management of power

fault conditions.

Both signals are asserted low to the PXA27x processor inputs. They can be used to place the

processor into sleep or deep sleep power-down modes to reduce power quickly and to preserve as

much system state or context as possible. Entry into sleep or deep sleep can be initiated directly by

the PXA27x processor PMU hardware upon assertion of nBATT_FAULT and nVDD_FAULT, or

these events can trigger a software exception handler that saves the system state and issues the

command to enter sleep or deep sleep. The PXA27x processor power manager PMCR[BIDAE] and

PMCR[VIDAE]

control bits select between hardware or software handling of these respective

fault events.

7.1 nVDD_FAULT

nVDD_FAULT signals the PXA27x processor that one or more of its currently enabled supplies

are below the minimum regulation limit (supplies that are not enabled do not cause nVDD_FAULT

assertion). Functionally, nVDD_FAULT signals the processor when it is safe to exit sleep or when

it must enter sleep (using the mechanism selected by the PMCR[VIDAE] setting). nVDD_FAULT

is ignored after a wakeup event until the SYS_DEL and PWR_DEL timers expires. The PXA27x

processor also has a configuration bit

that allows nVDD_FAULT to be ignored in sleep mode.

1. See the Intel® PXA27x Processor Family Developer’s Manual

2. The PSLR[IVF] bit; see the Intel® PXA27x Processor Family Developer’s Manual