Personal Computer User Manual

Intel® PXA27x Processor Family Power Requirements

30 Application Note

• I

C programmable output voltage ramp rate with a default/reset ramp rate of 10mV/µs. Refer

to the Intel® PXA27x Processor Family EMTS for ramp rate specifications

The VCC_CORE regulator must support a minimum set of these six output voltages: 0.85, 0.95,

1.1, 1.2, 1.3, 1.4 and 1.55 V. It is preferable to provide more voltage steps by dividing the range

between 0.85 V and 1.55 V using a step size of 10 to 50 mV. The accuracy of each voltage set point

must be at least ± 1 voltage step. When using more than the minimum set of five steps it is not

necessary to support these five exact step values.

The VCC_CORE regulator must also support programming the voltage ramp rate over a one-

decade range of the nominal default value (10mV per µs). Ramping is accomplished via a smooth

analog ramp driven by an internal ramp generator, or through a series of microsteps of 10-25 mV

per microstep, which are performed sequentially after a small delay to make up the requested

change in voltage. Faster ramp rates can, in practice, be limited by the capabilities of the regulator

and by the amount of bulk capacitance on the VCC_CORE supply.

Controlling the core voltage is accomplished by loading registers in the PMIC via the I

C serial

bus. The bus transfers data one byte at a time to the PMIC. Register loads are 8 bits wide, although

not all bits need be used by accompanying circuitry. If voltage ramps are comprised of a series of

microsteps, the step rate can be programmed as increments of the PMIC internal oscillator used by

its voltage converters. Many switching regulators use oscillators in the 500 kHz to 1 MHz range.

Section 8.0 contains more information on the recommended PMIC register set and bit fields.

The worst-case load, or maximum di/dt (from the slowest run mode setting to the fastest turbo

mode setting) expected is 200 mA per 10 ns.

Note: It may be advantageous to allow scaling of the VCC_CORE domain above 1.55V for debug

purposes, which would require the PMIC and associated power circuitry being able to drive

VCC_CORE up to 2.0V.

6.2 Intel® PXA27x Processor Voltage Manager

The PXA27x processor power manager unit (PMU) includes an internal voltage manager unit with

a dedicated I

C interface and a command sequencer. The I

C interface provides the PXA27x

processor with dynamic and static voltage control capability, using an I

C module for

communicating with the external PMIC. The voltage manager provides these features:

• Static (Halted) or dynamic (operational) voltage change

• Up to 32 I

C commands automatically sent to I

• Single and multi-byte I

C command support

• The PXA27x processor I

C commands are user defined to match the format defined by the

PMIC.

• Programmable delay between commands

1. A step-down, or voltage dropping converter