Personal Computer User Manual

Intel® PXA27x Processor Family Power Requirements
Application Note 29
Note: If the PMIC does not disable VCC_CORE, VCC_PLL, or VCC_SRAM when PWR_EN is de-
asserted, the PMIC must not disable any of the regulators controlled by SYS_EN when SYS_EN is
de-asserted to ensure that supply sequencing requirements are satisfied.
A wakeup event must occur to exit deep sleep. The wakeup event can include the following:
• A transition on one of the deep sleep wakeup-capable GPIOs that has been programmed to
respond to an edge or level change
• An interrupt from a timer in the real-time clock unit
Upon exiting from deep-sleep mode, the processor returns to the last clock frequency prior to deep-
sleep mode entry. Likewise, the PMIC must also be able to return to the previous voltage level
prior to entering deep-sleep mode. The PMIC must accommodate the appropriate voltage level
upon exiting.
The PXA27x processor asserts SYS_EN to the PMIC and starts its SYS_DEL timer. The PMIC
turns on its high-voltage supplies (VCC_IO, VCC_LCD, VCC_USIM, VCC_BB, VCC_USB, and
VCC_MEM). After waiting the period set by SYS_DEL, the processor asserts PWR_EN to the
PMIC and starts its PWR_DEL countdown timer. The PMIC turns on the low-voltage supplies
(VCC_CORE, VCC_SRAM, and VCC_PLL) and de-asserts nVDD_FAULT when all supplies are
stable and within regulation. If nVDD_FAULT is not de-asserted before the PWR_DEL timer
expires, the PXA27x processor returns the system to deep-sleep mode; otherwise, the PXA27x
processor completes the sleep-reset boot sequence.
Note: If the nBATT_FAULT signal asserts in sleep or deep sleep, all wake-up events are ignored until
nBATT_FAULT is de-asserted.
If the deep-sleep configuration is set and PSLR[PSSD] (sleep mode shorten wakeup delay disable
bit) is set, the PXA27x processor shortens the wakeup sequence by asserting PWR_EN as soon as
the PXA27x processor PMU detects all the corresponding power supplies have powered up, as
shown in Figure 4. Refer to the Intel® PXA27x Processor Family EMTS manual for deep-sleep
entry and exit timing specifications.
6.0 Dynamic Voltage Management (DVM)
The PXA27x processor has a number of features that enable the dynamic management of power
consumption, which is based on the computing power required at any particular time. These
features enable the processor to modify the core frequency voltage of the processor during
operation, dynamically matching the computing performance to the current computing workload.
A system combining the PXA27x processor, a power management integrated circuit (PMIC), and
supporting DVM software can run a wide range of applications using only a fraction of the battery
power that would be required running at the fixed frequency and voltage needed for the peak
computing workload.
6.1 VCC_CORE Regulator and Dynamic Voltage Management
The PMIC must have these minimum features for its VCC_CORE regulator to support dynamic
voltage and frequency management:
• High-efficiency I
2
C programmable buck
1
converter output providing VCC_CORE in the
voltage range 0.85-1.55 V (-5%/10%) with a default/reset output in the same range.