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Intel® PXA27x Processor Family Power Requirements

26 Application Note

Note: 1) nRESET_OUT assertion is software programmable during processor resets. Refer to the Intel®

PXA27x Processor Family Developer’s Manual.

Figure 4. Intel® PXA27x Processor Power Manager Sleep Reset State Diagram

Normal

Run

Mode

Deep

Sleep

Deep

Sleep

Batt fault

Wakeup

while

Batt Fault

asserted

wakeup

Wakeup

while

Batt Fault

de-asserted

wakeup = 1 &

= 1 &

nBATT_FAULT = 0

nBATT_FAULT = 1

(Software initiated

nBATT_FAULT = 0

nBATT_FAULT = 1

wakeup

= 1 &

nBATT_FAULT = 0

wakeup = 1 &

nBATT_FAULT = 1

SYS_EN = 1

nBATT_FAULT = 1

Count

Down

SYS_DEL

Count

Down

PWR_DEL

(count_done = 1 & nBATT_FAULT = 1) OR

(all_vcc_hi = 1 & PSSD = 1 & nBATT_FAULT = 1)

PWR_EN = 1

(nBATT_FAULT = 1 & nVDD_FAULT = 1) &

(count_done = 1 OR all_vcc_low = 1 & PSSD = 1)

Assert

pwr_

enable

nBATT_FAULT = 0

(nVDD_FAULT = 0) & (count_done = 1)

Initial

Power

clk_32k_ok = 1

Enable

PLL

pll_ok = 1

All external IO pads use

VCC_IO or corresponding power

supply. Power manager continues

to use VCC_BATT

nVDD_FAULT = 0

deep sleep) OR