Personal Computer User Manual

Intel® PXA27x Processor Family Power Requirements
Application Note 25
1. The PMIC asserts nRESET.
2. The PXA27x processor asserts the nRESET_OUT
1
signal. The time between nRESET
assertion and nRESET_OUT assertion depends on whether this event the PXA27x processor
was previously running or whether this is an initial power up event.
3. The PMIC de-asserts nRESET after a minimum of 50 ms from nRESET assertion.
4. The internal processor PMU waits for the 13.000 MHz oscillator and internal PLLs to
stabilize, if needed.
5. The PXA27x processor de-asserts the nRESET_OUT signal.
The timing for hardware reset is shown in the Intel® PXA27x Processor Family Electrical,
Mechanical, and Thermal Specification. The PXA27x processor power manager sleep reset state is
shown in Figure 4. The timing between nRESET assertion and nRESET_OUT assertion is shown
in the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification data
sheet.