Personal Computer User Manual

Intel® PXA27x Processor Family Power Requirements
Application Note 17
3.0 Intel® PXA27x Processor Low Power Operating
Modes
The PXA27x processor provides several low-power operating modes that temporarily suspend or
power down the core or peripherals to reduce power consumption. The external power supplies are
disabled in some modes. Transitions between certain domains require a sequence of events and
handshakes between the PXA27x processor and the external power management integrated circuit
(PMIC) that are detailed in this section.
The PXA27x processor supports six operating modes, shown in Table 7.
The state diagram in Figure 3 shows the transitions between operating modes and the events and
conditions that cause or enable transitions.
Table 7. Intel® PXA27x Processor Operating Modes
Operating Modes Description
Normal mode
(Run/Turbo mode)
All external power supplies are enabled and all internal domains are powered. The CPU
core and peripherals are fully functional.
Idle mode The clocks to the CPU are disabled but context is retained. The peripherals continue
normal operation. All power supplies are enabled. An interrupt assertion causes the
transition back to normal mode.
Deep Idle mode The core frequency is at 13 MHz (CCCR[CDPIS] is set) and the processor is in idle
mode.
Standby mode The clocks to the CPU are disabled and the CPU is placed in a low leakage state but
context is retained. All external power supplies are enabled. Each internal SRAM bank
can be independently placed in a low-power mode where the state is retained but no
activity is allowed under program control. The PLLs are disabled and peripheral
operation is suspended. An interrupt assertion causes the transition back to normal
mode.
Sleep mode All internal power domains except VCC_RTC and VCC_OSC are optionally powered
down. All clock sources except the real-time clock (RTC) and power manager are
disabled, and all external low-voltage power supplies (VCC_CORE, VCC_PLL, and
VCC_SRAM) controlled by PWR_EN are disabled. Recovery is initiated by external
wake-up events or select internal wake-up events. A system reboot is required because
the program counter is invalid.
Deep sleep mode All internal power domains except VCC_RTC and VCC_OSC are powered down. All
clock sources except the real-time clock (RTC) and power manager are disabled, and the
external low-voltage supplies (VCC_CORE, VCC_PLL, and VCC_SRAM) controlled by
PWR_EN are disabled. The high-voltage power supplies (VCC_IO, VCC_MEM,
VCC_LCD, VCC_BB and VCC_USIM) controlled by SYS_EN are disabled. The active
internal power domains are powered from one of three internal regulators driven from the
backup battery signal, VCC_BATT. Recovery is initiated by external or select internal
wake-up events and requires a system reboot, because the program counter is invalid.
NOTE: Refer to the Intel® PXA27x Processor Family
Developers Manual, “Clocks and Power” section for
more information on low power modes