Intel® PXA27x Processor Family Power Requirements Application Note Order Number: 280005-002
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Intel® PXA27x Processor Family Power Requirements Contents Contents 1.0 Introduction....................................................................................................................................5 1.1 2.0 Naming Conventions ............................................................................................................ 5 Intel® PXA27x Processor Power Supply Domains..................................................................... 5 2.1 2.
Intel® PXA27x Processor Family Power Requirements Contents 7.2 8.0 nBATT_FAULT ................................................................................................................... 32 Power Management Integrated Circuit Requirements ............................................................. 32 8.1 8.2 8.3 9.0 General PMIC Characteristics ............................................................................................ 32 Features of a PMIC....................................
Intel® PXA27x Processor Family Power Requirements 1.0 Introduction The Intel® PXA27x Processor Family (PXA27x processor) is a highly integrated system-on-chip optimized for handheld battery-powered devices such as PDAs and 2.5G or 3G cell phones. The PXA27x processor is ideal for products requiring substantial computing and multimedia capability with very low power consumption. The PXA27x processor combines a high-performance CPU with a variety of integrated peripheral functions.
Intel® PXA27x Processor Family Power Requirements The terms run mode and normal mode are used interchangeably, although normal mode comprises both the run-mode and turbo-mode settings. 2.0 Intel® PXA27x Processor Power Supply Domains Viewed externally, the main or backup battery powers ten power-supply domains. Additional supply domains are present internally, but power for these is derived from the external supply inputs.
Intel® PXA27x Processor Family Power Requirements Figure 1. Intel® PXA27x Processor Internal and External Power Domains VCC_SRAM CPU MEM Control P-PLL 312 M VCC_PER VCC_OSC LCD Control SRAM Control TXTAL 32.768 k USB-H 48.000 M DMA/ Bridge DC-DC VCC_R3 L1 SRAM 3 VCC_REG CPM 32.768 k ICP 48.000 M VCC_RTC VCC_R2 I2 S prg. frq. SRAM 2 RTC 32.768 k MMC 19.500 M VCC_R1 PWR_I2C 13 M SRAM 1 VCC_PI BB 48.000 M VCC_R0 Timer 13 M SRAM 0 USIM 48.
Intel® PXA27x Processor Family Power Requirements 2.1 Power Domains and System Voltage/Current Requirements The following sections document the power requirements for the PXA27x processor, but do not include external support, memory, or other peripheral components. The power consumption values shown in Table 5 are all worst-case numbers. These numbers give the worst-case system power-supply requirements and do not reflect typical system power consumption. 2.1.
Intel® PXA27x Processor Family Power Requirements Table 2. Intel® PXA27x Processor Voltage Domains (Sheet 1 of 2) Voltage VCC_BATT Description BATTERY VOLTAGE: Voltage-limited power from the main battery, or directly from a backup battery, at nominal 3.0 V (±25%). VCC_BATT must be supplied to start the power manager.
Intel® PXA27x Processor Family Power Requirements Table 2. Intel® PXA27x Processor Voltage Domains (Sheet 2 of 2) Voltage VCC_IO Description Fixed 3.0 V or 3.3 V (±10%) for standard CMOS I/Os interfacing to external components, which are also supplied from fixed 3.0 V or 3.3 V. The I/Os for external components connected to the corresponding signals on the PXA27x processor must be supplied from the same regulator.
Intel® PXA27x Processor Family Power Requirements Table 3. Regulators Required to Power the Intel® PXA27x Processor Regulator Description 1 Regulated main battery voltage, nominally 3.0 V (limited to a maximum of 3.75 V) to power VCC_BATT and charge the optional backup battery also connected to VCC_BATT. 2 VCC_IO, VCC_LCD, VCC_MEM, VCC_BB, VCC_USB connected together (can be powered at 3.0V or 3.3 V (±10%)). 3 VCC_USIM at 1.8V and 3.
Intel® PXA27x Processor Family Power Requirements Note: Table 4. The figures in Table 4 where taken from a system with no enhanced power management optimization such as Intel Wireless Speedstep (which allows control over the PXA27x processors low power modes and dynamically selectable frequency and voltage change capability). Intel® PXA27x Processor VCC_CORE Supply Current Frequency Point @ voltage V Dhrystones 2.
Intel® PXA27x Processor Family Power Requirements Table 5. Intel® PXA27x Processor Supply Current For Each Power Domain Current (mA) @ voltage V Power (mW) Power manager and real-time clock max. during power-on and sleep wakeup 10 @ 3.75 V 37.5 Power manager and real-time clock typical during deep sleep 6 µA @ 3.0 V 20 µW Name VCC_BATT VCC_IO Functional Units Peripheral input/output 25 @ 3.3 V 82.5 VCC_LCD LCD input/output 11 @ 3.3 V 33 VCC_MEM (3.
Intel® PXA27x Processor Family Power Requirements these supplies must come up at the required voltage to operate reliably and to avoid damage to the external components. VCC_IO must be the highest potential of the system I/O supplies1. VCC_IO can be connected to any of VCC_LCD, VCC_MEM, VCC_USIM, VCC_USB and VCC_BB, but none of these supplies can exceed VCC_IO.
Intel® PXA27x Processor Family Power Requirements Table 6. Possible Backup Battery Configurations Backup Battery Connection Description VCC_BATT and PMIC The backup battery connects to both the VCC_BATT input and PMIC charging regulator (driven from the main battery or AC adaptor supply). Powering VCC_BATT from a battery directly eliminates the inefficiency of an external regulator in the PMIC, maximizing the battery life in sleep and deep sleep.
Intel® PXA27x Processor Family Power Requirements Figure 2.
Intel® PXA27x Processor Family Power Requirements 3.0 Intel® PXA27x Processor Low Power Operating Modes The PXA27x processor provides several low-power operating modes that temporarily suspend or power down the core or peripherals to reduce power consumption. The external power supplies are disabled in some modes.
Intel® PXA27x Processor Family Power Requirements Figure 3.
Intel® PXA27x Processor Family Power Requirements Table 8.
Intel® PXA27x Processor Family Power Requirements 4.4 Power Manager I2C Data (PWR_SDA) / GPIO<4>) The PWR_SDA signal is the power manager I2C data signal to the external PMIC. It functions like an open-drain signal so either component can pull it down to a logic-low level. 4.5 System-Level Considerations for I2C Both I2C signals have an alternate function on the PXA27x processor as GPIO signals.
Intel® PXA27x Processor Family Power Requirements assertion of nRESET for a minimum of 50 ms. This type of reset would be used only for a severe and otherwise unrecoverable hardware or software problem, because it completely resets the state of the processor and may result in lost data. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for the hardware reset timing specification. 4.6.
Intel® PXA27x Processor Family Power Requirements The PXA27x processor has a low-power DC-to-DC converter that is enabled by software while in sleep or deep-sleep mode. Enabling the low-power DC-to-DC converter further reduces power consumption by shutting off the high-power regulators on the PMIC, eliminating losses in the external power supply subsystem. Use of the sleep mode DC-to-DC converter requires three external capacitors connected to the PXA27x processor PWR_CAP signals.
Intel® PXA27x Processor Family Power Requirements 5.1.2 Initial Power Up and Deep Sleep Exit Sequence As shown in Figure 2, the external power management integrated circuit (PMIC) supplies both high-voltage (I/O) and low-voltage (internal) power to the PXA27x processor. The external voltage regulator also sources nBATT_FAULT and nVDD_FAULT signals to the PXA27x processor.
Intel® PXA27x Processor Family Power Requirements Note: The nRESET signal must be asserted earlier in the reset sequence for the processor. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on reset timing specifications. The sequence for initial (start-of-life) power-on reset is as follows: 1. VCC_BATT power is applied to the processor and reaches a stable voltage of at least 2.
Intel® PXA27x Processor Family Power Requirements 1. The PMIC asserts nRESET. 2. The PXA27x processor asserts the nRESET_OUT1 signal. The time between nRESET assertion and nRESET_OUT assertion depends on whether this event the PXA27x processor was previously running or whether this is an initial power up event. 3. The PMIC de-asserts nRESET after a minimum of 50 ms from nRESET assertion. 4. The internal processor PMU waits for the 13.000 MHz oscillator and internal PLLs to stabilize, if needed. 5.
Intel® PXA27x Processor Family Power Requirements Note: 1) nRESET_OUT assertion is software programmable during processor resets. Refer to the Intel® PXA27x Processor Family Developer’s Manual. Figure 4.
Intel® PXA27x Processor Family Power Requirements 5.2 Sleep and Deep Sleep The sleep and deep-sleep modes reduce power consumption by powering down most units in the PXA27x processor. However, the real-time clock, timekeeping oscillator (32.768 kHz), and PMU circuits remain active. The processor oscillator (13.000 MHz), power manager I2C, and JTAG units may also be active.
Intel® PXA27x Processor Family Power Requirements The processor commands entry into sleep mode by de-asserting PWR_EN to the PMIC once the PMIC and system are prepared. The PMIC responds by turning off the specified set of supplies along with VCC_CORE, VCC_PLL, and VCC_SRAM. For entry into sleep mode, there is no requirement for how long these supplies require to shut down after de-assertion of PWR_EN.
Intel® PXA27x Processor Family Power Requirements Note: If the PMIC does not disable VCC_CORE, VCC_PLL, or VCC_SRAM when PWR_EN is deasserted, the PMIC must not disable any of the regulators controlled by SYS_EN when SYS_EN is de-asserted to ensure that supply sequencing requirements are satisfied. A wakeup event must occur to exit deep sleep.
Intel® PXA27x Processor Family Power Requirements • I2C programmable output voltage ramp rate with a default/reset ramp rate of 10mV/µs. Refer to the Intel® PXA27x Processor Family EMTS for ramp rate specifications The VCC_CORE regulator must support a minimum set of these six output voltages: 0.85, 0.95, 1.1, 1.2, 1.3, 1.4 and 1.55 V. It is preferable to provide more voltage steps by dividing the range between 0.85 V and 1.55 V using a step size of 10 to 50 mV.
Intel® PXA27x Processor Family Power Requirements 6.3 Power Manager I2C Interface The PXA27x processor communicates with the PMIC using the I2C serial bus. The flexible I2C controller in the processor can pre-load a buffer with a series of commands, or multi-byte commands of any size, up to a total of 32 bytes of command address and data.
Intel® PXA27x Processor Family Power Requirements System designers can include a software-controlled threshold level detection for nVDD_FAULT to allow an optional SDRAM keep-alive capability. 7.2 nBATT_FAULT nBATT_FAULT indicates that the main battery is low or has been removed from the device, giving the PXA27x processor an indication that power will shortly cease.
Intel® PXA27x Processor Family Power Requirements Table 9. General PMIC Characteristics Characteristic Highly Integrated, Multi-Function 8.2 Description Incorporating buck, boost, buck-boost, and LDO regulators for the PXA27x processor and surrounding system elements, with dynamic voltage management (DVM) logic for the core supply. It includes power-up, power-down, and sleep mode power sequencing, and generates correct nRESET, nBATT_FAULT, and nVDD_FAULT outputs for the system.
Intel® PXA27x Processor Family Power Requirements • USB on-the-go charge pump which generates +5.0 V (optional) The following analog/mixed-signal features are required in many handheld or battery-powered systems, and it is a good idea to provide them in a highly integrated PMIC: • • • • • • • • • • 8.
Intel® PXA27x Processor Family Power Requirements 8.3.3 DVM Control and Status Register 3 The Control and Status registers contain the GO bit which, once set, activates the voltage change requested by the new voltage in DVM Control register 1, at the ramp rate specified in DVM Control register 2. Additional bits can be added to this register to provide the status for system regulators whose voltage is configured by strapping hardware control signals. 8.3.
Intel® PXA27x Processor Family Power Requirements 36 Application Note
