User manual

Hardware Reference Manual 327
Intel
®
IXP2800 Network Processor
PCI Unit
9.2.5.5 Target Read Accesses from the PCI Bus
A PCI read occurs if the PCI address matches one of the base address registers and the PCI
command is either a Memory Read, Memory Read Line, or Memory Read Multiple.
The read is completed as a PCI delayed read. That is, on the first occurrence of the read, the PCI
unit signals a retry to the PCI master,. If there is no prior read pending, the PCI unit latches the
address and command and places it into the target address FIFO. When the address reaches the
head of the FIFO, the PCI unit reads the DRAM. Subsequent reads will also get retry responses
until data is available.
When the read data is returned into the PCI Read FIFO, the PCI unit begins to decrement its
discard timer. If the PCI bus master has not repeated the read by the time the timer reaches 0, the
PCI unit discards the read data, invalidates the delayed read address and sets Discard Timer
Expired (bit 16) in the Control register (PCI_CONTROL). If enabled, the PCI unit interrupts the
Intel XScale
®
core. The discard timer counts 2
15
(32,768) PCI clocks.
When the master repeats the read command, the PCI unit compares the address and checks that the
command is a Memory Read, a Memory Read Line, or a Memory Read Multiple. If there is a
match, the response is as follows:
• If the read data has not yet been read, the response is retry.
• If the read data has been read, assert trdy_l and deliver the data. If the master attempts to
continue the burst past the amount of data read, the PCI unit signals a target disconnect.
• CSR reads are always 32-bit reads.
• If the discard timer has expired for a read, the subsequent read will be treated as a new read.
9.2.6 PCI Initiator Transactions
PCI master transactions are caused by either the Intel XScale
®
core loads and stores that fall into
the various PCI address spaces, Microengine read and write commands, or by the DMA engine.
The command register (PCI_COMMAND) bus master bit (BUS_MASTER) must be set for the
PCI unit to perform any of the initiator transactions.
The PCI cycle is initiated when there is an entry in the PCI Core Interface initiator address FIFO.
The core handshakes with the master interface with the FBus FIFO status signals. The PCI core
supports both burst and non-burst master read transfers by the burst count inputs
(FB_BstCntr[7:0]), driven by Master Interface to inform the core the burst size. For a Master write,
FB_WBstonN indicates to the PCI core whether the transfers are burst or non-burst, on a 64-bit
double Dword basis.
The PCI core supports read and write memory cycles as an initiator while taking care of all
disconnect/retry situations on the PCI Bus.
9.2.6.1 PCI Request Operation
If an external arbiter is used (PCI_CFG_ARB[1] is not active), the reql[0] and gnt[0] are connected
to the PCI_REQ_L and PCI_GNT_L pins. Otherwise, they are connected to the internal arbiter.
The PCI unit asserts req_l[0] to act as a bus master on the PCI. If gnt_l[0] is asserted, the PCI unit
can start a PCI transaction regardless of the state of req_l[0]. When the PCI unit requests the PCI
bus, it performs a PCI transaction when gnt_l[0] is received. Once req_l[0] is asserted, the PCI unit