User manual

Hardware Reference Manual 261
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.2.8.2 CSIX
8.2.8.2.1 Horizontal Parity
The receive logic computes Horizontal Parity on each 16 bits of each received Cword (there is a
separate parity for data received on rising and falling edge of the clock).
There is an internal HP Error Flag. At the end of each CFrame, the flag is reset. As each 16 bits of
each Cword is received, the expected odd-parity value is computed from the data, and compared to
the value received on RxPar. If there is a mismatch, the flag is set. The value of the flag becomes
the element status HP Err bit.
If the HP Error Flag is set:
• the FC_Egress_Status[SF_CReady] and FC_Egress_Status[SF_DReady] bits are cleared
• the MSF_Interrupt_Status[HP_Error] bit is set (which can interrupt the Intel XScale
®
core
if enabled)
8.2.8.2.2 Vertical Parity
The receive logic computes Vertical Parity on CFrames.
There is a VP Error Flag and a 16-bit VP Accumulator register. At the end of each CFrame, the flag
is reset and the register is cleared. As each Cword is received, odd parity is accumulated in the
register as defined in the CSIX specification (16 bits of vertical parity are formed on 32 bits of
received data by treating the data as words; i.e., bit 0 and bit 16 of the data are accumulated into
parity bit 0, bit 1, and bit 17 of the data are accumulated into parity bit 1, etc.). After the entire
CFrame has been received (including the Vertical Parity field; the two bytes following the Payload)
the accumulated value should be 0xFFFF. If it is not, the VP Error Flag is set. The value of the flag
becomes the element status VP Err bit.
Note: The Vertical Parity always follows the Payload, which may include padding to the CWord width if
the Payload Length field is not an integral number of CWords. The CWord width is programmed in
MSF_Rx_Control[Rx_CWord_Size].
If the VP Error Flag is set:
• the FC_Egress_Status[SF_CReady] and FC_Egress_Status[SF_DReady] bits are cleared
• the MSF_Interrupt_Status[VP_Error] bit is set (which can interrupt the Intel XScale
®
core)
8.2.9 Error Cases
Receive errors are specific to the protocol, SPI-4 or CSIX. The element status, described in
Table 90 and Table 91, has appropriate error bits defined. Also, there are some IXP2800 Network
Processor specific error cases — for example, when an mpacket arrives with no free elements —
that are logged in the MSF_Interrupt_Status register, which can interrupt the Intel XScale
®
core
if enabled.