User manual

174 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Microengines
4.1.4.2 Absolute Addressing Mode
With Absolute addressing, any GPR can be read or written by any one of the eight Contexts in a
Microengine. Absolute addressing enables register data to be shared among all of the Contexts,
e.g., for global variables or for parameter passing. All 256 GPRs can be read by Absolute address.
4.1.4.3 Indexed Addressing Mode
With Indexed addressing, any Transfer or Next Neighbor register can be read or written by any one
of the eight Contexts in an Microengine. Indexed addressing enables register data to be shared
among all of the Contexts. For indexed addressing the register number comes from the T_Index
register for Transfer registers or NN_Put and NN_Get registers (for Next Neighbor registers).
4.2 Local CSRs
Local Control and Status registers (CSRs) are external to the Execution Datapath, and hold specific
purpose information. They can be read and written by special instructions (local_csr_rd and
local_csr_wr) and are typically accessed less frequently than datapath registers. Because Local
CSRs are not built in the datapath, there is a write to use delay of either three or four cycles, and a
read to consume penalty of one cycle.
4.3 Execution Datapath
The Execution Datapath can take one or two operands, perform an operation, and optionally write
back a result. The sources and destinations can be GPRs, Transfer registers, Next Neighbor
registers, and Local Memory. The operations are shifts, addition, subtraction, logicals,
multiplication, byte-align, and “find first bit set”.
4.3.1 Byte Align
The datapath provides a mechanism to move data from source register(s) to any destination
register(s) with byte aligning. Byte aligning takes four consecutive bytes from two concatenated
values (eight bytes), starting at any of four byte boundaries (0, 1, 2, 3), and based on the endian
type (which is defined in the instruction opcode), as shown in Table 58. The four bytes are taken
from two concatenated values. Four bytes are always supplied from a temporary register that
always holds the A or B operand from the previous cycle, and the other four bytes from the B or A
operand of the Byte Align instruction. The operation is described below using the block diagram
Figure 58. The alignment is controlled by the two LSBs of the Byte_Index Local CSR.
Table 58. Align Value and Shift Amount
Align Value
(in Byte_Index[1:0])
Right Shift Amount (Number of Bits in Decimal)
Little-Endian Big-Endian
0032
1824
21616
3248