User manual

106 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.6.5 Write Buffer/Fill Buffer Operation and Control
The write buffer is always enabled, which means stores to external memory will be buffered. The
K bit in the Auxiliary Control register (CP15, register 1) is a global enable/disable for allowing
coalescing in the write buffer. When this bit disables coalescing, no coalescing will occur
regardless the value of the page attributes. If this bit enables coalescing, the page attributes X, C,
and B are examined to see if coalescing is enabled for each region of memory.
All reads and writes to external memory occur in program order when coalescing is disabled in the
write buffer. If coalescing is enabled in the write buffer, writes may occur out of program order to
external memory. Program correctness is maintained in this case by comparing all store requests
with all the valid entries in the fill buffer.
The write buffer and fill buffer support a drain operation, such that before the next instruction
executes, all the Intel XScale
®
core data requests to external memory have completed.
Writes to a region marked non-cacheable/non-bufferable (page attributes C, B, and X all 0) will
cause execution to stall until the write completes.
If software is running in a privileged mode, it can explicitly drain all buffered writes.
3.7 Configuration
The System Control Coprocessor (CP15) configures the MMU, caches, buffers and other system
attributes. Where possible, the definition of CP15 follows the definition of the StrongARM*
products. Coprocessor 14 (CP14) contains the performance monitor registers and the trace buffer
registers.
CP15 is accessed through MRC and MCR coprocessor instructions and allowed only in privileged
mode. Any access to CP15 in user mode or with LDC or STC coprocessor instructions will cause
an undefined instruction exception.
CP14 registers can be accessed through MRC, MCR, LDC, and STC coprocessor instructions and
allowed only in privileged mode. Any access to CP14 in user mode will cause an undefined
instruction exception.
The Intel XScale
®
core Coprocessors, CP15 and CP14, do not support access via CDP, MRRC, or
MCRR instructions. An attempt to access these coprocessors with these instructions will result in
an Undefined Instruction exception.
Many of the MCR commands available in CP15 modify hardware state sometime after execution.
A software sequence is available for those wishing to determine when this update occurs.
Like certain other ARM* architecture products, the Intel XScale
®
core includes an extra level of
virtual address translation in the form of a PID (Process ID) register and associated logic.
Privileged code needs to be aware of this facility because, when interacting with CP15, some
addresses are modified by the PID and others are not.
An address that has yet to be modified by the PID (“PIDified”) is known as a virtual address (VA).
An address that has been through the PID logic, but not translated into a physical address, is a
modified virtual address (MVA). Non-privileged code always deals with VAs, while privileged
code that programs CP15 occasionally needs to use MVAs. For details refer to the Intel XScale
®
Core Developers Manual.