Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
26 Specification Update
X25. Machine Check Exception May Occur When Interleaving Code between
Different Memory Types
Problem: A small window of opportunity exists where code fetches interleaved between different
memory types may cause a machine check exception. A complex set of micro-
architectural boundary conditions is required to expose this window.
Implication: Interleaved instruction fetches between different memory types may result in a
machine check exception. The system may hang if machine check exceptions are
disabled. Intel has not observed the occurrence of this erratum while running
commercially available applications or operating systems.
Workaround: Software can avoid this erratum by placing a serializing instruction between code
fetches between different memory types.
Status: For the steppings affected, see the Summary of Tables of Changes.
X26. Split I/O Writes Adjacent to Retry of APIC End of Interrupt (EOI)
Request May Cause Livelock Condition
Problem: When Split I/O instruction writes occur adjacent to a retry of a Local APIC End of
Interrupt (EOI) request by the chipset, a livelock condition may result. The required
sequences of events are:
1. The processor issues a Local APIC EOI message.
2. The chipset responds with a retry because its downstream ports are full. It
expects the processor to return with the same EOI request.
3. The processor issues a Split I/O write instruction instead.
4. The chipset responds with a retry because it expected the APIC EOI.
5. The processor insists the Split I/O write instruction must be completed and issues
write instruction again.
Implication: A processor livelock may occur causing a system hang. This issue has only been
observed in synthetic lab testing conditions and has not been seen in any
commercially available applications. The erratum does not occur with Intel mobile
chipset based platforms.
Workaround: Use the PIC instead of the APIC for the interrupt controller.
Status: For the steppings affected, see the Summary of Tables of Changes.
X27. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4-G
limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur, the system may not issue a #GP fault.
Workaround: Software should ensure that memory accesses do not occur above the 4-G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary of Tables of Changes.