Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

INDEX
INDEX-8 Vol. 2B
PSUBUSW instruction, 4-198
PSUBW instruction, 4-187
PUNPCKHBW instruction, 4-202
PUNPCKHDQ instruction, 4-202
PUNPCKHQDQ instruction, 4-202
PUNPCKHWD instruction, 4-202
PUNPCKLBW instruction, 4-207
PUNPCKLDQ instruction, 4-207
PUNPCKLQDQ instruction, 4-207
PUNPCKLWD instruction, 4-207
PUSH instruction, 4-212
PUSHA instruction, 4-217
PUSHAD instruction, 4-217
PUSHF instruction, 4-220
PUSHFD instruction, 4-220
PXOR instruction, 4-223
R
RC (rounding control) field, x87 FPU control word,
3-333, 3-342, 3-384
RCL instruction, 4-226
RCPPS instruction, 4-233
RCPSS instruction, 4-236
RCR instruction, 4-226
RDMSR instruction, 4-239, 4-242, 4-246
CPUID flag, 3-174
RDPMC instruction, 4-241
RDTSC instruction, 4-246
Reg/opcode field, instruction format, 2-4
Related literature, 1-8
Remainder, x87 FPU operation, 3-360
REP/REPE/REPZ/REPNE/REPNZ prefixes, 3-136,
3-462, 4-18, 4-248
Reserved
use of reserved bits, 1-4
RET instruction, 4-253
REX prefixes
addressing modes, 2-11
and INC/DEC, 2-10
encodings, 2-10, B-2
field names, 2-11
ModR/M byte, 2-10
overview, 2-9
REX.B, 2-10
REX.R, 2-10
REX.W, 2-10
special encodings, 2-13
RIP-relative addressing, 2-14
ROL instruction, 4-226
ROR instruction, 4-226
Rounding, round to integer, x87 FPU operation, 3-366
RPL field, 3-63
RSM instruction, 4-265
RSQRTPS instruction, 4-267
RSQRTSS instruction, 4-270
R/m field, instruction format, 2-4
S
SAL instruction, 4-275
SAR instruction, 4-275
SBB instruction, 3-541, 4-282
Scale (operand addressing), 2-4
Scale, x87 FPU operation, 3-375
Scan string instructions, 4-286
SCAS instruction, 4-250, 4-286
SCASB instruction, 4-286
SCASD instruction, 4-286
SCASW instruction, 4-286
Segment
descriptor, segment limit, 3-550
limit, 3-550
registers, moving values to and from, 3-592
selector, RPL field, 3-63
Segmented addressing, 1-6
Self Snoop, 3-176
SETcc instructions, 4-290
SF (sign) flag, EFLAGS register, 3-30
SFENCE instruction, 4-294
SGDT instruction, 4-295
SHAF instruction, 4-273
Shift instructions, 4-275
SHL instruction, 4-275
SHLD instruction, 4-298
SHR instruction, 4-275
SHRD instruction, 4-301
SHUFPD instruction, 4-304
SHUFPS instruction, 4-307
SIB byte, 2-4
32-bit addressing forms of, 2-8
description of, 2-4
SIDT instruction, 4-295, 4-310
Significand, extracting from floating-point number,
3-426
SIMD floating-point exceptions, unmasking, effects
of, 3-520
Sine, x87 FPU operation, 3-377, 3-379
SLDT instruction, 4-313
SMSW instruction, 4-315
SpeedStep technology, 3-172
SQRTPD instruction, 4-318
SQRTPS instruction, 4-321
SQRTSD instruction, 4-324
SQRTSS instruction, 4-327
Square root, Fx87 PU operation, 3-382
SS register, 3-522, 3-593, 4-128
SSE extensions
cacheability instruction encodings, B-68
CPUID flag, 3-175
floating-point encodings, B-60
instruction encodings, B-60
integer instruction encodings
, B-66
memory ordering encodings, B-68
SSE2 extensions
cacheability instruction encodings, B-85
CPUID flag, 3-175