Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-158 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PSHUFLW—Shuffle Packed Low Words
Description
Copies words from the low quadword of the source operand (second operand) and
inserts them in the low quadword of the destination operand (first operand) at word
locations selected with the order operand (third operand). This operation is similar to
the operation used by the PSHUFD instruction, which is illustrated in Figure 4-7. For
the PSHUFLW instruction, each 2-bit field in the order operand selects the contents of
one word location in the low quadword of the destination operand. The binary encod-
ings of the order operand fields select words (0, 1, 2, or 3) from the low quadword of
the source operand to be copied to the destination operand. The high quadword of
the source operand is copied to the high quadword of the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. The order operand is an 8-bit immediate. Note
that this instruction permits a word in the low quadword of the source operand to be
copied to more than one word location in the low quadword of the destination
operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[15:0] ← (SRC >> (ORDER[1:0] ∗ 16))[15:0];
DEST[31:16] ← (SRC
>> (ORDER[3:2] ∗ 16))[15:0];
DEST[47:32] ← (SRC
>> (ORDER[5:4] ∗ 16))[15:0];
DEST[63:48] ← (SRC
>> (ORDER[7:6] ∗ 16))[15:0];
DEST[127:64] ← SRC[127:64];
Intel C/C++ Compiler Intrinsic Equivalent
PSHUFLW __m128i _mm_shufflelo_epi16(__m128i a, int n)
Flags Affected
None.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
F2 0F 70 /r ib PSHUFLW xmm1,
xmm2/m128, imm8
Valid Valid Shuffle the low words in
xmm2/m128 based on the
encoding in imm8 and store
the result in xmm1.