Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-153
INSTRUCTION SET REFERENCE, N-Z
Operation
DEST[31:0] ← (SRC >> (ORDER[1:0] ∗ 32))[31:0];
DEST[63:32] ← (SRC
>> (ORDER[3:2] ∗ 32))[31:0];
DEST[95:64] ← (SRC
>> (ORDER[5:4] ∗ 32))[31:0];
DEST[127:96] ← (SRC
>> (ORDER[7:6] ∗ 32))[31:0];
Intel C/C++ Compiler Intrinsic Equivalent
PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
Real-Address Mode Exceptions
#GP(0) If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
If any part of the operand lies outside of the effective address
space from 0 to FFFFH.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.