Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-73
INSTRUCTION FORMATS AND ENCODINGS
mem to xmmreg 0110 0110:0000 1111:0101 1011: mod xmmreg r/m
CVTTPS2DQ—Convert With
Truncation Packed Single-Precision
Floating-Point Values to Packed
Doubleword Integers
xmmreg to xmmreg 1111 0011:0000 1111:0101 1011:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0101 1011: mod xmmreg r/m
CVTDQ2PS—Convert Packed
Doubleword Integers to Packed
Double-Precision Floating-Point
Values
xmmreg to xmmreg 0000 1111:0101 1011:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1011: mod xmmreg r/m
DIVPD—Divide Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1110:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1110: mod xmmreg r/m
DIVSD—Divide Scalar Double-
Precision Floating-Point Values
xmmreg to xmmreg 1111 0010:0000 1111:0101 1110:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:0101 1110: mod xmmreg r/m
MAXPD—Return Maximum Packed
Double-Precision Floating-Point
Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1111:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1111: mod xmmreg r/m
MAXSD—Return Maximum Scalar
Double-Precision Floating-Point Value
xmmreg to xmmreg 1111 0010:0000 1111:0101 1111:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:0101 1111: mod xmmreg r/m
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding