Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-277
INSTRUCTION SET REFERENCE, N-Z
Description
Shifts the bits in the first operand (destination operand) to the left or right by the
number of bits specified in the second operand (count operand). Bits shifted beyond
the destination operand boundary are first shifted into the CF flag, then discarded. At
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
D0 /5 SHR r/m8,1 Valid Valid Unsigned divide r/m8 by 2,
once.
REX + D0 /5 SHR r/m8**, 1 Valid N.E. Unsigned divide r/m8 by 2,
once.
D2 /5 SHR r/m8, CL Valid Valid Unsigned divide r/m8 by 2,
CL times.
REX + D2 /5 SHR r/m8**, CL Valid N.E. Unsigned divide r/m8 by 2,
CL times.
C0 /5 ib SHR r/m8, imm8 Valid Valid Unsigned divide r/m8 by 2,
imm8 times.
REX + C0 /5 ib SHR r/m8**,
imm8
Valid N.E. Unsigned divide r/m8 by 2,
imm8 times.
D1 /5 SHR r/m16, 1 Valid Valid Unsigned divide r/m16 by 2,
once.
D3 /5 SHR r/m16, CL Valid Valid Unsigned divide r/m16 by 2,
CL times
C1 /5 ib SHR r/m16, imm8 Valid Valid Unsigned divide r/m16 by 2,
imm8 times.
D1 /5 SHR r/m32, 1 Valid Valid Unsigned divide r/m32 by 2,
once.
REX.W + D1 /5 SHR r/m64, 1 Valid N.E. Unsigned divide r/m64 by 2,
once.
D3 /5 SHR r/m32, CL Valid Valid Unsigned divide r/m32 by 2,
CL times.
REX.W + D3 /5 SHR r/m64, CL Valid N.E. Unsigned divide r/m64 by 2,
CL times.
C1 /5 ib SHR
r/m32, imm8 Valid Valid Unsigned divide r/m32 by 2,
imm8 times.
REX.W + C1 /5 ib SHR r/m64, imm8 Valid N.E. Unsigned divide r/m64 by 2,
imm8 times.
NOTES:
* Not the same form of division as IDIV; rounding is toward negative infinity.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix
is used: AH, BH, CH, DH.
***See IA-32 Architecture Compatibility section below.