Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B INDEX-7
INDEX
P
P6 family processors
description of, 1-1
machine encodings, B-59
PABSB instruction, 4-22
PABSD instruction, 4-22
PABSW instruction, 4-22
PACKSSDW instruction, 4-26
PACKSSWB instruction, 4-26
PACKUSWB instruction, 4-30
PADDB instruction, 4-33
PADDD instruction, 4-33
PADDQ instruction, 4-37
PADDSB instruction, 4-40
PADDSW instruction, 4-40
PADDUSB instruction, 4-44
PADDUSW instruction, 4-44
PADDW instruction, 4-33
PALIGNR instruction, 4-48
PAND instruction, 4-51
PANDN instruction, 4-54
PAUSE instruction, 4-57
PAVGB instruction, 4-58
PAVGW instruction, 4-58
PCE flag, CR4 register, 4-242
PCMPEQB instruction, 4-61
PCMPEQD instruction, 4-61
PCMPEQW instruction, 4-61
PCMPGTB instruction, 4-65
PCMPGTD instruction, 4-65
PCMPGTW instruction, 4-65
PE (protection enable) flag, CR0 register, 3-539
Pending break enable, 3-176
Pentium 4 processor, 1-1
Pentium II processor, 1-2
Pentium III processor, 1-2
Pentium Pro processor, 1-2
Pentium processor, 1-1
Pentium processor family processors
machine encodings, B-53
Performance-monitoring counters
CPUID inquiry for, 3-180
reading, 4-241
PEXTRW instruction, 4-70
PHADDD instruction, 4-73
PHADDSW instruction, 4-76
PHADDW instruction, 4-73
PHSUBD instruction, 4-79
PHSUBSW instruction, 4-82
PHSUBW instruction, 4-79
Pi, 3-342
PINSRW instruction, 4-85, 4-163
PMADDUBSW instruction, 4-88
PMADDUDSW instruction, 4-88
PMADDWD instruction, 4-91
PMAXSW instruction, 4-95
PMAXUB instruction, 4-98
PMINSW instruction, 4-101
PMINUB instruction, 4-104
PMOVMSKB instruction, 4-107
PMULHRSW instruction, 4-110
PMULHUW instruction, 4-113
PMULHW instruction, 4-117
PMULLW instruction, 4-120
PMULUDQ instruction, 4-124
POP instruction, 4-127
POPA instruction, 4-134
POPAD instruction, 4-134
POPF instruction, 4-136
POPFD instruction, 4-136
POPFQ instruction, 4-136
POR instruction, 4-140
PREFETCHh instruction, 4-143
Prefixes
Address-size override prefix, 2-2
Branch hints, 2-2
branch hints, 2-2
instruction, description of, 2-2
legacy prefix encodings, B-2
LOCK, 2-2, 3-541
Operand-size override prefix, 2-2
REP or REPE/REPZ, 2-2
REPNE/REPNZ, 2-2
REP/REPE/REPZ/REPNE/REPNZ, 4-248
REX prefix encodings, B-2
Segment override prefixes, 2-2
PSADBW instruction, 4-145
Pseudo-functions
VMfail, 5-2
VMfailInvalid, 5-2
VMfailValid, 5-2
VMsucceed, 5-2
PSHUFB instruction, 4-149
PSHUFD instruction, 4-152
PSHUFHW instruction, 4-155
PSHUFLW instruction, 4-158
PSHUFW instruction, 4-161
PSIGNB instruction, 4-163
PSIGND instruction, 4-163
PSIGNW instruction, 4-163
PSLLD instruction, 4-170
PSLLDQ instruction, 4-168
PSLLQ instruction, 4-170
PSLLW instruction, 4-170
PSRAD instruction
, 4-175
PSRAW instruction, 4-175
PSRLD instruction, 4-182
PSRLDQ instruction, 4-180
PSRLQ instruction, 4-182
PSRLW instruction, 4-182
PSUBB instruction, 4-187
PSUBD instruction, 4-187
PSUBQ instruction, 4-191
PSUBSB instruction, 4-194
PSUBSW instruction, 4-194
PSUBUSB instruction, 4-198