Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-75
INSTRUCTION FORMATS AND ENCODINGS
xmmreg1 to xmmreg2 1111 0010:0000 1111:0001 0000:11 xmmreg1
xmmreg2
xmmreg1 to mem 1111 0010:0000 1111:0001 0000: mod xmmreg r/m
MOVUPD—Move Unaligned Packed
Double-Precision Floating-Point
Values
xmmreg2 to xmmreg1 0110 0110:0000 1111:0001 0001:11 xmmreg2
xmmreg1
mem to xmmreg1 0110 0110:0000 1111:0001 0001: mod xmmreg r/m
xmmreg1 to xmmreg2 0110 0110:0000 1111:0001 0000:11 xmmreg1
xmmreg2
xmmreg1 to mem 0110 0110:0000 1111:0001 0000: mod xmmreg r/m
MULPD—Multiply Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 1001:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 1001: mod xmmreg rm
MULSD—Multiply Scalar Double-
Precision Floating-Point Values
xmmreg to xmmreg 1111 0010:00001111:01011001:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:00001111:01011001: mod xmmreg r/m
ORPD—Bitwise Logical OR of
Double-Precision Floating-Point
Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 0110:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 0110: mod xmmreg r/m
SHUFPD—Shuffle Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 0110 0110:0000 1111:1100 0110:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 0110 0110:0000 1111:1100 0110: mod xmmreg r/m:
imm8
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding