Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-54 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
B.4 64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD
INSTRUCTION EXTENSIONS
Non-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3
are covered by applying these rules to Table B-19 through Table B-30. Table B-32
lists special encodings (instructions that do not follow the rules below).
1. The REX instruction has no effect:
• On immediates
• If both operands are MMX registers
• On MMX registers and XMM registers
• If an MMX register is encoded in the reg field of the ModR/M byte
2. If a memory operand is encoded in the r/m field of the ModR/M byte, REX.X and
REX.B may be used for encoding the memory operand.
3. If a general-purpose register is encoded in the r/m field of the ModR/M byte,
REX.B may be used for register encoding and REX.W may be used to encode the
64-bit operand size.
4. If an XMM register operand is encoded in the reg field of the ModR/M byte, REX.R
may be used for register encoding. If an XMM register operand is encoded in the
r/m field of the ModR/M byte, REX.B may be used for register encoding.
B.5 MMX INSTRUCTION FORMATS AND ENCODINGS
MMX instructions, except the EMMS instruction, use a format similar to the 2-byte
Intel Architecture integer format. Details of subfield encodings within these formats
are presented below.
B.5.1 Granularity Field (gg)
The granularity field (gg) indicates the size of the packed operands that the instruc-
tion is operating on. When this field is used, it is located in bits 1 and 0 of the second
opcode byte. Table B-18 shows the encoding of the gg field.
Table B-18. Encoding of Granularity of Data Field (gg)
gg Granularity of Data
00 Packed Bytes
01 Packed Words
10 Packed Doublewords
11 Quadword