Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-48 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

SMSW – Store Machine Status Word

to register 0100 000B 0000 1111 : 0000 0001 : 11 100

reg

to memory 0100 00XB 0000 1111 : 0000 0001 : mod

100 r/m

STC – Set Carry Flag 1111 1001

STD – Set Direction Flag 1111 1101

STI – Set Interrupt Flag 1111 1011

STOS/STOSB/STOSW/STOSD/STOSQ – Store

String Data

store string data 1010 101w

store string data (RAX at address RDI) 0100 1000 1010 1011

STR – Store Task Register

to register 0100 000B 0000 1111 : 0000 0000 : 11 001

reg

to memory 0100 00XB 0000 1111 : 0000 0000 : mod

001 r/m

SUB – Integer Subtraction

register1 from register2 0100 0R0B 0010 100w : 11 reg1 reg2

byteregister1 from byteregister2 0100 0R0B 0010 1000 : 11 bytereg1

bytereg2

qwordregister1 from qwordregister2 0100 1R0B 0010 1000 : 11 qwordreg1

qwordreg2

register2 from register1 0100 0R0B 0010 101w : 11 reg1 reg2

byteregister2 from byteregister1 0100 0R0B 0010 1010 : 11 bytereg1

bytereg2

qwordregister2 from qwordregister1 0100 1R0B 0010 1011 : 11 qwordreg1

qwordreg2

memory from register 0100 00XB 0010 101w : mod reg r/m

memory8 from byteregister 0100 0RXB 0010 1010 : mod bytereg r/m

memory64 from qwordregister 0100 1RXB 0010 1011 : mod qwordreg r/m

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding