Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-25

INSTRUCTION FORMATS AND ENCODINGS

immediate8 to memory64 0100 10XB : 1000 0031 : mod 010 r/m : imm8

ADD – Add

register1 to register2 0100 0R0B : 0000 000w : 11 reg1 reg2

qwordregister1 to qwordregister2 0100 1R0B 0000 0000 : 11 qwordreg1

qwordreg2

register2 to register1 0100 0R0B : 0000 001w : 11 reg1 reg2

qwordregister1 to qwordregister2 0100 1R0B 0000 0010 : 11 qwordreg1

qwordreg2

memory to register 0100 0RXB : 0000 001w : mod reg r/m

memory64 to qwordregister 0100 1RXB : 0000 0000 : mod qwordreg r/m

qwordregister to memory64 0100 1RXB : 0000 0011 : mod qwordreg r/m

immediate to register 0100 0000B : 1000 00sw : 11 000 reg :

immediate data

immediate32 to qwordregister 0100 100B : 1000 0001 : 11 010 qwordreg :

imm

immediate to AL, AX, or EAX 0000 010w : immediate8

immediate to RAX 0100 1000 : 0000 0101 : imm32

immediate to memory 0100 00XB : 1000 00sw : mod 000 r/m :

immediate

immediate32 to memory64 0100 10XB : 1000 0001 : mod 010 r/m :

imm32

immediate8 to memory64 0100 10XB : 1000 0011 : mod 010 r/m : imm8

AND – Logical AND

register1 to register2 0100 0R0B 0010 000w : 11 reg1 reg2

qwordregister1 to qwordregister2 0100 1R0B 0010 0001 : 11 qwordreg1

qwordreg2

register2 to register1 0100 0R0B 0010 001w : 11 reg1 reg2

register1 to register2 0100 1R0B 0010 0011 : 11 qwordreg1

qwordreg2

memory to register 0100 0RXB 0010 001w : mod reg r/m

memory64 to qwordregister 0100 1RXB : 0010 0011 : mod qwordreg r/m

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding