Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-16 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
register from DR6-DR7 0000 1111 : 0010 0001 : 11 eee reg
register from DR4-DR5 0000 1111 : 0010 0001 : 11 eee reg
register from DR0-DR3 0000 1111 : 0010 0001 : 11 eee reg
MOV – Move to/from Segment Registers
register to segment register 1000 1110 : 11 sreg3 reg
register to SS 1000 1110 : 11 sreg3 reg
memory to segment reg 1000 1110 : mod sreg3 r/m
memory to SS 1000 1110 : mod sreg3 r/m
segment register to register 1000 1100 : 11 sreg3 reg
segment register to memory 1000 1100 : mod sreg3 r/m
MOVS/MOVSB/MOVSW/MOVSD – Move Data
from String to String
1010 010w
MOVSX – Move with Sign-Extend
register2 to register1 0000 1111 : 1011 111w : 11 reg1 reg2
memory to reg 0000 1111 : 1011 111w : mod reg r/m
MOVZX – Move with Zero-Extend
register2 to register1 0000 1111 : 1011 011w : 11 reg1 reg2
memory to register 0000 1111 : 1011 011w : mod reg r/m
MUL – Unsigned Multiply
AL, AX, or EAX with register 1111 011w : 11 100 reg
AL, AX, or EAX with memory 1111 011w : mod 100 reg
NEG – Two's Complement Negation
register 1111 011w : 11 011 reg
memory 1111 011w : mod 011 r/m
NOP – No Operation 1001 0000
NOP – Multi-byte No Operation
1
register 0000 1111 0001 1111 : 11 000 reg
memory 0000 1111 0001 1111 : mod 000 r/m
NOT – One's Complement Negation
register 1111 011w : 11 010 reg
Table B-13. General Purpose Instruction Formats and Encodings
for Non-64-Bit Modes (Contd.)
Instruction and Format Encoding